Add an erase command to let the user have more control over the
allocated area. This will also be more familiar to embedded developers.
As a bonus it minimizes the logic needed in firmware, and in theory we
can now increase the current write limit of one sector.
- `digest` is an array and hence the address of the first element is
returned.
- This will keep it more consistent with the rest of the code base.
- Fixed misspelled comment.
* -abc2, run two passes of 'abc' for slightly improved logic density
* -device u, optimize timing for up5k device
* -dff, run 'abc'/'abc9' with -dff (D flip flop) option
Update digest of application_fpga.bin
Flags:
--indentation_spaces=2
--wrap_end_else_clauses=true
Verify flag, used in checkfmt, only returns error if the last file is
not formatted, temporary fix implemented with grep.
* Break long lines and use tab to indent
* Remove use of "tee" since it messes up the return status
* Remove the generated application_fpga_par.json if nextpnr-ice40 fails
on timing.
* Change log file ending from .log to .txt
* Fix some spacing
The removal is coordinated and approved by YosysHQ, and are removed
to keep our headers uniform. These files were written on behalf of
Tillitis.
Two typos was corrected as well.
- Remove the define `NOCONSOLE`, add define `QEMU_CONSOLE`
- Inverse the use of it, add the define to have QEMU debug output in fw.
- Add a make target `qemu_firmware.elf` which builds the firmware with
QEMU console enabled.
Co-authored-by: Mikael Ågren <mikael@tillitis.se>
Move the logic implementing the RAM address and data
scrambling, descrambling into the RAM module. This cleans up
the top level, and makes it easier to change the scrambling
without chaning the top. In order to do correct scrambling the
address to the RAM core must be 16 bits, not 15.
Clean up some minor details at the top level, fixing text
aligment and grouping of ports in instances.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
Add API address to trigger system reset.
When written to will send system_reset signal
to the reset generator, which then perform a complete
reset cycle of the FPGA system.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
- Remove DUT variables from state display that was removed as part of
performance fix
- Corrected some incorrect display statements for expected unique ID and
byte counters
Co-authored-by: Daniel Jobson <jobson@tillitis.se>
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
Update:
- README
- testbench
- Symbolic names and variables in fw
- registers
- port name and wires
- Update fpga and fw digests
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
Remove the preceeding zero in the constant expression
that cause the simulator to warn about incorrect
bit size.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
