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0454e023cd · Ignore application_fpga_par.json · Updated 2024-04-25 09:29:47 +00:00
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Branches

fix_lint_uds_core

5a396d7f51 · Add model for SB_LUT4 to allow linting · Updated 2024-04-25 12:12:48 +00:00
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219_change_names_ram_random

a0eb82fe34 · Merge branch 'main' into 219_change_names_ram_random · Updated 2024-04-25 09:20:29 +00:00
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minimal_spi_master_rebase

fdea1bdfcd · Adding testbench and simulation targets for the SPI master. · Updated 2024-04-25 08:48:40 +00:00
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199-add-support-for-host-based-device-reset

bd45d3b0dd · Move reset control and status into the tk1 core · Updated 2024-04-22 14:14:10 +00:00
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js_xorwow_mem_init

2302c5130d · format code · Updated 2024-04-22 14:13:44 +00:00
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186_disable_cdi_access

d620ab1a03 · Write to CDI in app mode blocks read access · Updated 2024-04-22 14:13:12 +00:00
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add_finger_present

32837fe031 · Add finger present API and bit. Update README · Updated 2024-04-22 14:08:39 +00:00
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ci_checkhashes_in_new_job

a5e30f1203 · CI: Divide into separate jobs. · Updated 2024-04-19 10:16:41 +00:00
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186_disable_cdi_access_orig

a17a413e81 · Write to CDI in app mode blocks read access · Updated 2024-04-16 08:29:21 +00:00
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Increased_clock_frequency

875ba08299 · Increase clock frequency to 21 MHz · Updated 2024-04-15 13:07:45 +00:00
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minimal_spi_master

32f7ebc7ad · Add flag to control of SPI master is included in build · Updated 2024-04-15 08:50:51 +00:00
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remove_version_strings

3cf218469c · hw/tool: UDI/UDS storage · Updated 2024-04-03 09:27:00 +00:00
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update-ci-action

e471c1a65c · Update CI action to checkout@v4 · Updated 2024-03-19 09:52:33 +00:00
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uwg30

bec34f0b11 · Build FPGA for the uwg30 wcsp package · Updated 2024-03-14 13:41:18 +00:00
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uart_tx_debug_pin

71d091fcd5 · Add tx debug port functionality with API controlled select · Updated 2024-02-05 18:12:51 +00:00
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blake2s

6e6c2ab3ca · Add blake2s core · Updated 2023-09-08 12:52:40 +00:00
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