Default Branch

main 66888a3756 · tb: Make uart selftesting · Updated 2024-12-09 07:55:43 -05:00

ZIP  TAR.GZ

Branches

cth c1c0ac35f4 · Fix off-by-one UART bitrate counter value that will make the RX sampling · Updated 2025-01-09 10:49:00 -05:00	0 10		ZIP  TAR.GZ
mem_access e7531dab7c · Add complete checks for invalid memory accesses · Updated 2024-12-20 07:20:18 -05:00	0 1		ZIP  TAR.GZ
ch552_hid_cdc 8eade9933c · Add incoming and outgoing CTS (Clear To Send) signals for the CH552 · Updated 2024-12-18 05:30:25 -05:00	0 7		ZIP  TAR.GZ
syscall_picorv32_irq 6023d97ba3 · PoC: Remove IRQ30 from fw/irqpoc_c_example · Updated 2024-12-17 12:14:26 -05:00	5 15		ZIP  TAR.GZ
uart_fix 3389d7ebf3 · Fix off-by-one UART bitrate counter value that will make the RX sampling · Updated 2024-12-17 05:50:23 -05:00	0 1		ZIP  TAR.GZ
syscall_jmp_to_address_to_enable_fw_mode_persist c7e44d3575 · Update tk1/README and fpga README regarding system mode · Updated 2024-12-09 07:26:42 -05:00	5 7		ZIP  TAR.GZ
persistant_storage_fw_ 8c073c3d01 · fw: adapt fw syscall to hw syscall implementation · Updated 2024-12-09 03:01:34 -05:00	22 27		ZIP  TAR.GZ
syscall_jmp_to_address_to_enable_fw_mode_persist_tests ff495f0015 · WIP: Add tests for new access restrictions · Updated 2024-11-22 09:21:07 -05:00	22 10		ZIP  TAR.GZ
pc_based_access_control_spi_2_sycalls_fur_alle fd357a2534 · (fpga) Add API register for syscall trampoline address. · Updated 2024-11-15 08:16:37 -05:00	66 7		ZIP  TAR.GZ
pc_based_access_control_spi_2 90c94ce821 · fpga: Include SPI master during linting · Updated 2024-11-15 08:13:23 -05:00	66 3		ZIP  TAR.GZ
update_to_24_mhz_clock_freq 1651a1a666 · Update PicoRV32 clock frequency to 24 MHz · Updated 2024-11-04 05:26:41 -05:00	42 1		ZIP  TAR.GZ
uwg30 5b32cf2500 · Revise pins for SPI and RGB · Updated 2024-10-30 08:11:00 -04:00	40 2		ZIP  TAR.GZ
new_targets 80e18a7edc · Introduce a build script that leads you through the entire process · Updated 2024-10-09 07:36:10 -04:00	89 2		ZIP  TAR.GZ
syscall_poc fe8350422f · (fpga) Possibly working syscall hw functionality. · Updated 2024-08-29 09:02:04 -04:00	66 2		ZIP  TAR.GZ
free_running_timer 6bc061d160 · (doc) Update timer README with info about reached flag. · Updated 2024-08-21 07:47:36 -04:00	69 13		ZIP  TAR.GZ
fw_ram_4k_poc 1ce3085843 · fpga: Fix width of assigned fw_address · Updated 2024-07-11 08:34:10 -04:00	69 2		ZIP  TAR.GZ
spi_test_fw 56e108808e · fix bug in size · Updated 2024-07-10 06:42:41 -04:00	74 19		ZIP  TAR.GZ
udi_poc e5eabec19a · fpga: Expose PID, VID info in UDI for apps · Updated 2024-07-08 03:35:50 -04:00	74 1		ZIP  TAR.GZ
spi_clk_two_cycles 6045aacadc · FPGA: Remove the NEXT state in SPI master FSM · Updated 2024-06-18 09:11:56 -04:00	83 4		ZIP  TAR.GZ
spi_clk_three_cycles 0e9df05ad0 · FPGA: Experimental increase in SPI clock frequency · Updated 2024-06-18 07:14:28 -04:00	83 3		ZIP  TAR.GZ