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tillitis-key/hw/application_fpga
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Daniel Jobson bf1ac5c237
Remove YosysHQ copyright and fix name typo 
The removal is coordinated and approved by YosysHQ, and are removed
to keep our headers uniform. These files were written on behalf of
Tillitis.
Two typos was corrected as well.
2024-09-30 15:01:31 +02:00
..
core Remove YosysHQ copyright and fix name typo 2024-09-30 15:01:31 +02:00
data A construction of a minimal SPI master. 2024-06-11 15:28:29 +02:00
fw fw: remove warning of missing prototypes when building with QEMU console 2024-09-19 16:52:04 +02:00
rtl FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
tb Rename to TK1 2022-10-26 09:20:02 +02:00
tools hw/tool: UDI/UDS storage 2024-04-03 11:27:00 +02:00
application_fpga.bin.sha256 FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
config.vlt Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal 2023-03-01 13:37:31 +01:00
firmware.bin.sha512 FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
Makefile fw: simplify how to enable QEMU debug in firmware. 2024-09-19 16:51:55 +02:00