mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-12-25 07:29:25 -05:00
Fix makefile lines and tee exit status problem
* Break long lines and use tab to indent * Remove use of "tee" since it messes up the return status * Remove the generated application_fpga_par.json if nextpnr-ice40 fails on timing. * Change log file ending from .log to .txt * Fix some spacing
This commit is contained in:
Jonas Thörnblad
parent
bf1ac5c237
commit
0ea0eeb967
1
.gitignore
vendored
1
.gitignore
vendored
@ -29,7 +29,6 @@
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/check.smt2
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/check.vcd
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synth.json
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synth.log
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synth.txt
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synth.v
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application_fpga_par.json
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@ -41,24 +41,46 @@ OBJCOPY ?= llvm-objcopy
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CC = clang
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CFLAGS = -target riscv32-unknown-none-elf -march=rv32iczmmul -mabi=ilp32 \
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-static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf \
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-fno-builtin-putchar -fno-builtin-memcpy -nostdlib -mno-relax -Wall \
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-Wpedantic -Wno-language-extension-token -flto -g
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CFLAGS = \
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-target riscv32-unknown-none-elf \
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-march=rv32iczmmul \
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-mabi=ilp32 \
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-static \
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-std=gnu99 \
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-O2 \
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-ffast-math \
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-fno-common \
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-fno-builtin-printf \
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-fno-builtin-putchar \
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-fno-builtin-memcpy \
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-nostdlib \
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-mno-relax \
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-Wall \
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-Wpedantic \
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-Wno-language-extension-token \
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-flto \
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-g
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AS = clang
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ASFLAGS = -target riscv32-unknown-none-elf -march=rv32iczmmul -mabi=ilp32 -mno-relax
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ASFLAGS = \
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-target riscv32-unknown-none-elf \
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-march=rv32iczmmul \
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-mabi=ilp32 \
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-mno-relax
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ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
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# FPGA specific source files.
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FPGA_SRC = $(P)/rtl/application_fpga.v \
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$(P)/core/clk_reset_gen/rtl/clk_reset_gen.v
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FPGA_SRC = \
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$(P)/rtl/application_fpga.v \
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$(P)/core/clk_reset_gen/rtl/clk_reset_gen.v
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# Verilator simulation specific source files.
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VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
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$(P)/tb/reset_gen_vsim.v
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VERILATOR_FPGA_SRC = \
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$(P)/tb/application_fpga_vsim.v \
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$(P)/tb/reset_gen_vsim.v
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# Common verilog source files.
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VERILOG_SRCS = \
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@ -143,7 +165,7 @@ secret:
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# Firmware generation.
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# Included in the bitstream.
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#-------------------------------------------------------------------
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LDFLAGS=-T $(P)/fw/tk1/firmware.lds
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LDFLAGS = -T $(P)/fw/tk1/firmware.lds
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$(FIRMWARE_OBJS): $(FIRMWARE_DEPS)
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$(TESTFW_OBJS): $(FIRMWARE_DEPS)
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@ -161,7 +183,19 @@ check:
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.PHONY: splint
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splint:
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splint -nolib -predboolint +boolint -nullpass -unrecog -infloops -initallelements -type -unreachable -unqualifiedtrans -fullinitblock $(FIRMWARE_SOURCES)
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splint \
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-nolib \
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-predboolint \
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+boolint \
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-nullpass \
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-unrecog \
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-infloops \
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-initallelements \
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-type \
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-unreachable \
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-unqualifiedtrans \
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-fullinitblock \
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$(FIRMWARE_SOURCES)
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testfw.elf: $(TESTFW_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(TESTFW_OBJS) $(LDFLAGS) -o $@
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@ -189,16 +223,21 @@ check-binary-hashes:
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$(OBJCOPY) --input-target=elf32-littleriscv --output-target=binary $< $@
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chmod -x $@
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#-------------------------------------------------------------------
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# Source linting.
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#-------------------------------------------------------------------
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LINT=verilator
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LINT = verilator
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# For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the
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# cell library.
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LINT_FLAGS = +1364-2005ext+ --lint-only \
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-Wall -Wno-DECLFILENAME -Wno-WIDTHEXPAND -Wno-UNOPTFLAT \
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--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
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LINT_FLAGS = \
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+1364-2005ext+ \
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--lint-only \
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-Wall \
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-Wno-DECLFILENAME \
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-Wno-WIDTHEXPAND \
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-Wno-UNOPTFLAT \
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--timescale 1ns/1ns \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS
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lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
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$(LINT) $(LINT_FLAGS) \
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@ -213,20 +252,27 @@ lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
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|| { cat lint_issues.txt; exit 1; }
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.PHONY: lint
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#-------------------------------------------------------------------
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# Build Verilator compiled simulation for the design.
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#-------------------------------------------------------------------
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verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS) \
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$(P)/tb/application_fpga_verilator.cc
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verilator --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS \
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-Wall -Wno-COMBDLY -Wno-lint \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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--cc --exe --Mdir verilated --top-module application_fpga \
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$(filter %.v, $^) $(filter %.cc, $^)
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verilator \
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--timescale 1ns/1ns \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS \
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-Wall \
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-Wno-COMBDLY \
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-Wno-lint \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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--cc \
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--exe \
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--Mdir verilated \
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--top-module application_fpga \
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$(filter %.v, $^) \
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$(filter %.cc, $^)
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make -C verilated -f Vapplication_fpga.mk
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.PHONY: verilator
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@ -258,17 +304,38 @@ tb:
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YOSYS_FLAG ?=
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synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
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$(YOSYS_PATH)yosys -v3 -l synth.log $(YOSYS_FLAG) -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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$(YOSYS_PATH)yosys \
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-v3 \
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-l synth.txt \
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$(YOSYS_FLAG) \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
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-p 'synth_ice40 -dsp -top application_fpga -json $@; write_verilog -attr2comment synth.v' \
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$(filter %.v, $^) |& tee $(patsubst %.json,%,$@).txt
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$(filter %.v, $^)
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application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
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$(NEXTPNR_PATH)nextpnr-ice40 --freq $(TARGET_FREQ) --ignore-loops --up5k --package sg48 --json $< \
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--pcf $(P)/data/$(PIN_FILE) --write $@ |& tee $(patsubst %.json,%,$@).txt
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$(NEXTPNR_PATH)nextpnr-ice40 \
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-l application_fpga_par.txt \
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--freq $(TARGET_FREQ) \
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--ignore-loops \
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--up5k \
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--package sg48 \
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--json $< \
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--pcf $(P)/data/$(PIN_FILE) \
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--write $@ \
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&& { exit 0; } \
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|| { rm -f application_fpga_par.json; exit 1; }
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application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex
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UDS_HEX="$(P)/data/uds.hex" UDI_HEX="$(P)/data/udi.hex" OUT_ASC=$@ $(NEXTPNR_PATH)nextpnr-ice40 --up5k --package sg48 --ignore-loops --json $< --run tools/patch_uds_udi.py
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UDS_HEX="$(P)/data/uds.hex" \
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UDI_HEX="$(P)/data/udi.hex" \
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OUT_ASC=$@ \
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$(NEXTPNR_PATH)nextpnr-ice40 \
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--up5k \
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--package sg48 \
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--ignore-loops \
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--json $< \
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--run tools/patch_uds_udi.py
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application_fpga.bin: application_fpga.asc bram_fw.hex firmware.hex
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$(ICESTORM_PATH)icebram -v bram_fw.hex firmware.hex < $< > $<.tmp
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@ -284,8 +351,11 @@ application_fpga_testfw.bin: application_fpga.asc bram_fw.hex testfw.hex
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# post-synthesis functional simulation.
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#-------------------------------------------------------------------
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synth_tb.vvp: $(P)/tb/tb_application_fpga.v synth.json
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iverilog -o $@ -s tb_application_fpga synth.v $(P)/tb/tb_application_fpga.v \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS $(ICE40_SIM_CELLS)
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iverilog \
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-o $@ \
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-s tb_application_fpga synth.v $(P)/tb/tb_application_fpga.v \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS \
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$(ICE40_SIM_CELLS)
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chmod -x $@
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synth_sim: synth_tb.vvp
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@ -348,7 +418,7 @@ view: tb_application_fpga_vcd
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#-------------------------------------------------------------------
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clean: clean_fw
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rm -f bram_fw.hex
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rm -f synth.{log,v,json,txt} route.v application_fpga.{asc,bin,vcd} application_fpga_testfw.bin
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rm -f synth.{v,json,txt} route.v application_fpga.{asc,bin,vcd} application_fpga_testfw.bin
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rm -f tb_application_fpga.vvp synth_tb.vvp route_tb.vvp
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rm -f application_fpga_par.{json,txt}
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rm -f *.vcd
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