Daniel Jobson 23b76b6178 Wip syscall function. ... PoC of how a syscall could look like.		2024-11-08 14:55:21 +01:00
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core	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
data	A construction of a minimal SPI master.	2024-06-11 15:28:29 +02:00
fw	Wip syscall function.	2024-11-08 14:55:21 +01:00
rtl	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
tb	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
tools	Add place and route script	2024-10-22 15:20:39 +02:00
application_fpga.bin.sha256	Add yosys flags to optimize synthesis	2024-10-22 12:46:12 +02:00
config.vlt	Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal	2023-03-01 13:37:31 +01:00
firmware.bin.sha512	FPGA: Move RAM address and data scrambling into the RAM module.	2024-08-30 10:53:13 +02:00
Makefile	Wip syscall function.	2024-11-08 14:55:21 +01:00