Jonas Thörnblad e04aacda48

Add make target to format verilog code using verible-verilog-format ...

Flags:
        --indentation_spaces=2
        --wrap_end_else_clauses=true

Verify flag, used in checkfmt, only returns error if the last file is
not formatted, temporary fix implemented with grep.

2024-10-22 12:04:19 +02:00

..

core

Include SPI master in default build

2024-10-16 12:50:32 +02:00

data

A construction of a minimal SPI master.

2024-06-11 15:28:29 +02:00

fw

fw: Fix erroneous type in frame header

2024-10-09 15:52:00 +02:00

rtl

Include SPI master in default build

2024-10-16 12:50:32 +02:00

tb

Rename to TK1

2022-10-26 09:20:02 +02:00

tools

hw/tool: UDI/UDS storage

2024-04-03 11:27:00 +02:00

application_fpga.bin.sha256

Include SPI master in default build

2024-10-16 12:50:32 +02:00

config.vlt

Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal

2023-03-01 13:37:31 +01:00

firmware.bin.sha512

FPGA: Move RAM address and data scrambling into the RAM module.

2024-08-30 10:53:13 +02:00

Makefile

Add make target to format verilog code using verible-verilog-format

2024-10-22 12:04:19 +02:00