tillitis-key/hw/application_fpga
Daniel Jobson deb29619bd
fw: remove address-of operator (&) where it is not needed
- `digest` is an array and hence the address of the first element is
  returned.
- This will keep it more consistent with the rest of the code base.
- Fixed misspelled comment.
2024-11-08 14:55:21 +01:00
..
core FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
data A construction of a minimal SPI master. 2024-06-11 15:28:29 +02:00
fw fw: remove address-of operator (&) where it is not needed 2024-11-08 14:55:21 +01:00
rtl FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
tb FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
tools Add place and route script 2024-10-22 15:20:39 +02:00
application_fpga.bin.sha256 Add yosys flags to optimize synthesis 2024-10-22 12:46:12 +02:00
config.vlt Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal 2023-03-01 13:37:31 +01:00
firmware.bin.sha512 FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
Makefile fw: break out trng and xorwow to rng.[ch] 2024-11-08 14:55:20 +01:00