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  • ded1e5f6a5
         Merge afa28ab1ad into 0454e023cd Daniel Jobson 2024-05-13 10:36:06 +0000
  • afa28ab1ad
         Adding testbench and simulation targets for the SPI master. minimal_spi_master_rebase Joachim Strömbergson 2024-04-18 14:16:11 +0200
  • 01a754c47c
         A construction of a minimal SPI master. Joachim Strömbergson 2023-05-16 16:14:21 +0200
  • 455e79070f
         Merge 32837fe031 into 0454e023cd Joachim Strömbergson 2024-04-29 09:03:00 +0200
  • e1bff221f7
         Merge bd45d3b0dd into 0454e023cd Joachim Strömbergson 2024-04-29 08:52:25 +0200
  • c3fe96ab88
         Merge 2302c5130d into 0454e023cd Joachim Strömbergson 2024-04-26 15:30:20 +0200
  • 1f0246e5e2
         Merge a0eb82fe34 into 0454e023cd Joachim Strömbergson 2024-04-26 10:44:43 +0200
  • 909dd0a5ed
         Merge d620ab1a03 into 0454e023cd Joachim Strömbergson 2024-04-25 17:47:09 +0200
  • e9cdc48e40
         Merge 5a396d7f51 into 0454e023cd Joachim Strömbergson 2024-04-25 12:29:38 +0000
  • 5a396d7f51
         Add model for SB_LUT4 to allow linting fix_lint_uds_core Joachim Strömbergson 2024-04-25 14:12:48 +0200
  • 0454e023cd
         Ignore application_fpga_par.json main Joachim Strömbergson 2024-04-25 11:29:47 +0200
  • a0eb82fe34
         Merge branch 'main' into 219_change_names_ram_random 219_change_names_ram_random Joachim Strömbergson 2024-04-25 11:20:29 +0200
  • 3a5d2d80fb
         Changing names for ram address and data randomization Joachim Strömbergson 2024-04-25 11:10:32 +0200
  • e961f46e79
         Update Verilog version to 2005 for linting Joachim Strömbergson 2024-04-22 11:07:58 +0200
  • bd45d3b0dd
         Move reset control and status into the tk1 core 199-add-support-for-host-based-device-reset Joachim Strömbergson 2024-04-04 14:46:14 +0200
  • 16eba3b8dd
         Trigger the original reset loop logic when host requests a reset Add comments to explain function and clean up heade, footer Joachim Strömbergson 2024-04-04 11:44:14 +0200
  • d6e0d90dfd
         First attempt at supporting host based reset Joachim Strömbergson 2024-04-03 13:51:34 +0200
  • 2302c5130d
         format code js_xorwow_mem_init dehanj 2024-04-05 08:25:26 +0200
  • 3ddd047994
         Just randomize the data, not the address Joachim Strömbergson 2024-04-05 08:00:17 +0200
  • 3dff3e6b4e
         Add experimental xowow based initial RAM scrambling Joachim Strömbergson 2024-04-04 15:27:31 +0200
  • d620ab1a03
         Write to CDI in app mode blocks read access 186_disable_cdi_access Joachim Strömbergson 2024-04-16 10:29:21 +0200
  • 4dbf31cc74
         Add API functionality to disable CDI access Joachim Strömbergson 2024-04-15 13:30:54 +0200
  • 32837fe031
         Add finger present API and bit. Update README add_finger_present Joachim Strömbergson 2024-04-22 15:35:31 +0200
  • f655196af7
         Clarify the functional description of the touch_sense core Joachim Strömbergson 2024-04-22 13:31:23 +0200
  • a5e30f1203
         CI: Divide into separate jobs. ci_checkhashes_in_new_job dehanj 2024-04-19 09:37:41 +0200
  • d7b8bb26a9
         CI: move check-hash to separate job. dehanj 2024-04-17 11:23:15 +0200
  • a17a413e81
         Write to CDI in app mode blocks read access 186_disable_cdi_access_orig Joachim Strömbergson 2024-04-16 10:29:21 +0200
  • 875ba08299
         Increase clock frequency to 21 MHz Increased_clock_frequency Joachim Strömbergson 2024-04-15 15:07:45 +0200
  • 4ab225714a
         Add API functionality to disable CDI access Joachim Strömbergson 2024-04-15 13:30:54 +0200
  • 32f7ebc7ad
         Add flag to control of SPI master is included in build minimal_spi_master Joachim Strömbergson 2024-04-15 10:50:51 +0200
  • 0aabebd71e
         Add conditional build of application_fpga with SPI-master Joachim Strömbergson 2024-04-09 12:53:37 +0200
  • 3cf218469c
         hw/tool: UDI/UDS storage remove_version_strings Michael Cardell Widerkrantz 2024-03-26 17:45:38 +0100
  • 1c90b1aa3d
         Add release notes for TK1-24.03 TK1-24.03 dehanj 2024-03-25 09:34:14 +0100
  • 574e17f26a
         Update hash of bitstream and firmware dehanj 2024-03-26 11:09:52 +0100
  • 4bd249816a
         fw: Remove unused header includes dehanj 2024-03-26 09:45:38 +0100
  • 3a6a60ff26
         fw: Protect zeroisation against compiler optimisation. dehanj 2024-02-02 14:20:21 +0100
  • c85b5311cd
         Change filename personalize.py to patch_uds_udi.py dehanj 2024-03-21 14:31:12 +0100
  • 88c6036215
         Add mitigations to threat model Michael Cardell Widerkrantz 2024-03-21 16:39:43 +0100
  • 0e166e4159
         Build tp1 firmware in CI dehanj 2024-03-20 12:42:47 +0100
  • 92136983c5
         Update hash of bitstream and firmware dehanj 2024-03-22 11:25:40 +0100
  • 09c1f3f549
         Silence splint somewhat Michael Cardell Widerkrantz 2024-03-21 12:32:08 +0100
  • b0efcf019e
         Include static analysis in CI Michael Cardell Widerkrantz 2024-03-21 12:11:33 +0100
  • d10c4972d7
         Use tkey-builder:4 tkey-builder-4 Michael Cardell Widerkrantz 2024-03-21 15:54:58 +0100
  • da40edfc51
         tkey-builder: Include clang-tidy & splint Michael Cardell Widerkrantz 2024-03-21 15:03:08 +0100
  • 48324fe5b3
         tp1 fw: Update pico-sdk to 1.5.1 Michael Cardell Widerkrantz 2024-03-21 14:17:01 +0100
  • 2ff2e9a91d
         fw: remove duplicate defines in tk1_mem.h dehanj 2024-03-21 10:28:51 +0100
  • 661a6458c8
         fw: Add missing TK1_MMIO_BASE Michael Cardell Widerkrantz 2024-03-21 10:09:38 +0100
  • 57a6ee2a12
         Use tkey-builder:3 as default when building tkey-builder-3 dehanj 2024-03-20 12:03:32 +0100
  • 8ca4241ade
         Disable non-zero exit for verilog linter in CI, see issue 182. dehanj 2024-03-20 10:47:37 +0100
  • de668a0244
         Clean up code and silence warnings after linting Joachim Strömbergson 2024-03-19 14:48:52 +0100
  • f364b523cf
         Change UDS address to three bits to match input port connection 'addr' Joachim Strömbergson 2024-03-19 13:57:17 +0100
  • bbde62d3f5
         Add PINMISSING lint ignore for I1 and I2 SB_LUT4 cells Joachim Strömbergson 2024-03-19 13:55:32 +0100
  • 8731908cb1
         Support incremental builds for the bitstream. Joachim Strömbergson 2023-11-28 10:20:30 +0100
  • 29fd8338a7
         Update the bitstream hash Joachim Strömbergson 2024-03-04 15:17:45 +0100
  • 8784a24b33
         Change cpu_monitor to security_monitor and to also check RAM Joachim Strömbergson 2024-03-19 13:17:14 +0100
  • 3fb6d66cf3
         Add set-only register for the force_trap signal to ensure that the device must be reset to get out of trap. This change also breaks a critical path. Joachim Strömbergson 2024-03-19 09:55:44 +0100
  • 4c3e210a00
         Only set ram_we to cpu_wstrb in RAM_PREFIX Joachim Strömbergson 2024-03-04 14:07:32 +0100
  • e48c0fc7d9
         Implement cs0 and cs1 as logic equations, not muxes Joachim Strömbergson 2024-03-18 14:41:52 +0100
  • 0590445f3d
         Add testbench targets on top-level Michael Cardell Widerkrantz 2024-03-20 12:15:38 +0100
  • ea9271292c
         Add Icarus Verilog compiler, simulator used by testbenches Joachim Strömbergson 2024-03-18 11:37:15 +0100
  • 159b5b052b
         Updated readme and docs to point at dev.tillitis.se. dehanj 2024-03-15 15:04:57 +0100
  • 4d4db70590
         fw: Change ASLR name in MMIO Michael Cardell Widerkrantz 2024-03-18 15:57:55 +0100
  • f40987b138
         fw: Change license for use with qemu Michael Cardell Widerkrantz 2024-03-18 15:20:16 +0100
  • c48724e115
         fw: Change memory constants to defines Michael Cardell Widerkrantz 2024-03-04 15:42:11 +0100
  • e471c1a65c
         Update CI action to checkout@v4 update-ci-action dehanj 2024-03-19 10:52:33 +0100
  • 1e34ddcfa6
         Update linter to Verilog-2005 dehanj 2024-03-19 10:45:37 +0100
  • 746d7f0e0d
         Use pedantic warnings Michael Cardell Widerkrantz 2024-03-04 15:57:29 +0100
  • e085d0ebd0
         Add void to function signatures meant to be used without args Michael Cardell Widerkrantz 2024-03-04 15:53:12 +0100
  • 046343e525
         Change memory constants to defines Michael Cardell Widerkrantz 2024-03-04 15:42:11 +0100
  • e2bd38c540
         fw: Remove unusued forever_redflash() Michael Cardell Widerkrantz 2024-03-18 16:19:59 +0100
  • 9d36acde08
         FW: Force the CPU to hang on errors dehanj 2024-03-14 15:07:42 +0100
  • bec34f0b11
         Build FPGA for the uwg30 wcsp package uwg30 Joachim Strömbergson 2023-12-21 13:49:58 +0100
  • fcccee8ec8
         Tkey-builder: Use Ubuntu-23.10, yosys-0.36 & nextpnr-0.6 Michael Cardell Widerkrantz 2023-12-07 18:06:11 +0100
  • 74d42d37ae
         Added instructions on what to do with the downloaded Winbond flash memory model to be able to build and run the SPI-master simulation Joachim Strömbergson 2024-02-20 09:51:37 +0100
  • 031f733984
         Removed the Winbond flash memory model. Added information in README on how to retrieve the Winbond memory model Joachim Strömbergson 2024-02-20 09:45:30 +0100
  • 784aa77092
         Add testcases and support tasks to berform read operations with the memory model attached to the DUT. We can read out device info and dump memory Joachim Strömbergson 2024-02-14 14:14:44 +0100
  • 7ba8a03595
         Adding more testcase that show that the dut works Joachim Strömbergson 2024-02-13 15:31:15 +0100
  • 5509be0eaa
         Adding information about the SPI-master including API and protocol, the memory type, and where to find the datasheet form the memory. Joachim Strömbergson 2024-02-12 13:38:07 +0100
  • 50f3e53a03
         Ignore the generated MEM.TXT memory init file for the Winbond Flash model Joachim Strömbergson 2024-02-12 13:11:25 +0100
  • 71d091fcd5
         Add tx debug port functionality with API controlled select uart_tx_debug_pin Joachim Strömbergson 2024-01-29 13:50:45 +0100
  • 844849b3ca
         Add script to generate hex file with data loaded into the memory model as content Joachim Strömbergson 2024-01-31 13:02:37 +0100
  • 8b27973129
         Integrate the Winbond memory model in the testbench and debug build of SPI master simulation Joachim Strömbergson 2024-01-31 09:06:02 +0100
  • a380911f5e
         Add Winbond flash memory model. Added note about the model in the README. Joachim Strömbergson 2024-01-31 09:02:34 +0100
  • d83f235fd3
         Add injection molded plastic case CASE-v3.0.0 dehanj 2023-12-07 14:21:24 +0100
  • 7019cd9048
         remove whitespaces and tabs dehanj 2023-11-14 09:33:02 +0100
  • 2014923966
         Isolate ringbuffer index, copy inbound usb data to new buffer dehanj 2023-11-07 12:52:44 +0100
  • 6d5da25321
         Translate + clean up dehanj 2023-11-07 10:21:57 +0100
  • f83abed4e4
         Add gpio for debug purpose dehanj 2023-11-06 12:19:00 +0100
  • 6e6c2ab3ca
         Add blake2s core blake2s Joachim Strömbergson 2023-09-08 14:52:40 +0200
  • 7f2efb68f9
         Inclulde the latest release tk1-23.03-2-Bellatrix dehanj 2023-09-06 11:16:28 +0200
  • bc661536dc
         Updating threat model with new section on TKey Unlocked Joachim Strömbergson 2023-08-30 11:23:54 +0200
  • a453aae031
         New plastic clip and update BOM for TP1 dehanj 2023-09-01 12:16:53 +0200
  • 5f0a9bec9a
         Add flash make podman target Michael Cardell Widerkrantz 2023-08-30 14:20:41 +0200
  • 7cd085a17e
         Avoid confusing errors by checking for programmer and stick first Daniel Lublin 2022-12-01 13:56:25 +0100
  • 426b56ebf5
         Verilog 2001 rule; use wires for assignments, not registers. (#139) blaufish 2023-08-16 10:44:18 +0200
  • cced6aec31
         Explicity make uart_core.rx_data a wire (#140) blaufish 2023-08-16 10:43:04 +0200
  • 244ec5bec5
         Explicity make uart_core.rx_data a wire blaufish 2023-08-15 16:08:56 +0200
  • 2bae13f1b0
         Verilog 2001 rule; use wires for assignments, not registers. blaufish 2023-08-15 12:18:30 +0200
  • 658ea4e20d
         Restore one sample register for MISO Joachim Strömbergson 2023-07-04 11:23:45 +0200
  • fef40a9ca1
         Reset rx_data register when SPI is not enabled Joachim Strömbergson 2023-07-04 09:17:37 +0200