Jonas Thörnblad 8af048fb9a Add yosys flags to optimize synthesis ... * -abc2, run two passes of 'abc' for slightly improved logic density * -device u, optimize timing for up5k device * -dff, run 'abc'/'abc9' with -dff (D flip flop) option Update digest of application_fpga.bin		2024-10-22 12:46:12 +02:00
..
core	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
data	A construction of a minimal SPI master.	2024-06-11 15:28:29 +02:00
fw	fw: Fix erroneous type in frame header	2024-10-09 15:52:00 +02:00
rtl	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
tb	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
tools	hw/tool: UDI/UDS storage	2024-04-03 11:27:00 +02:00
application_fpga.bin.sha256	Add yosys flags to optimize synthesis	2024-10-22 12:46:12 +02:00
config.vlt	Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal	2023-03-01 13:37:31 +01:00
firmware.bin.sha512	FPGA: Move RAM address and data scrambling into the RAM module.	2024-08-30 10:53:13 +02:00
Makefile	Add yosys flags to optimize synthesis	2024-10-22 12:46:12 +02:00