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FPGA: Increase clock frequency to 21 MHz

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-06-17 15:28:57 +02:00 committed by Daniel Jobson
parent 00599549e3
commit 75b028505f
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GPG Key ID: 3707A9DBF4BB8F1A
3 changed files with 9 additions and 9 deletions
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2
hw/application_fpga/application_fpga.bin.sha256
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@ -1 +1 @@
24e642b0dc78a7dbf4cd87c223dd26eefb1ad444c96858e1c2b373f35701ccc0 application_fpga.bin
42746c6d9d879ad975874fb51b3d4e031578dac9a0e7ddd4b10a1d3efa34c6c7 application_fpga.bin

6
hw/application_fpga/core/uart/rtl/uart.v
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@ -83,10 +83,10 @@ module uart(
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 18 MHz, 62500 bps
// Divisor = 18E6 / 62500 = 288
// Clock: 21 MHz, 62500 bps
// Divisor = 21E6 / 62500 = 336
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd288;
localparam DEFAULT_BIT_RATE = 16'd336;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;

10
hw/application_fpga/rtl/clk_reset_gen.v
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@ -70,14 +70,14 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//
// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
//
// Given the 12 MHz HFOSC clock set above, we get a final 18 MHz:
// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
//
// (12000000 * (47 + 1)) / (2^5 * (0 + 1)) = 18000000
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0101111), // DIVF = 47
.DIVQ(3'b101), // DIVQ = 5
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (
.RESETB(1'b1),