tillitis-key/hw/application_fpga
Jonas Thörnblad 0ea0eeb967
Fix makefile lines and tee exit status problem
* Break long lines and use tab to indent
* Remove use of "tee" since it messes up the return status
* Remove the generated application_fpga_par.json if nextpnr-ice40 fails
  on timing.
* Change log file ending from .log to .txt
* Fix some spacing
2024-10-08 16:07:17 +02:00
..
core Remove YosysHQ copyright and fix name typo 2024-09-30 15:01:31 +02:00
data A construction of a minimal SPI master. 2024-06-11 15:28:29 +02:00
fw fw: remove warning of missing prototypes when building with QEMU console 2024-09-19 16:52:04 +02:00
rtl FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
tb Rename to TK1 2022-10-26 09:20:02 +02:00
tools hw/tool: UDI/UDS storage 2024-04-03 11:27:00 +02:00
application_fpga.bin.sha256 FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
config.vlt Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal 2023-03-01 13:37:31 +01:00
firmware.bin.sha512 FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
Makefile Fix makefile lines and tee exit status problem 2024-10-08 16:07:17 +02:00