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tillitis-key/hw/application_fpga
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Jonas Thörnblad c6e8b6930c
Add place and route script 
Run multiple threads of nextpnr-ice40 to find a seed that gives a
layout that meets timing.
2024-10-22 15:20:39 +02:00
..
core
FPGA: Format verilog code
2024-10-22 12:04:19 +02:00
data
A construction of a minimal SPI master.
2024-06-11 15:28:29 +02:00
fw
fw: Fix erroneous type in frame header
2024-10-09 15:52:00 +02:00
rtl
FPGA: Format verilog code
2024-10-22 12:04:19 +02:00
tb
FPGA: Format verilog code
2024-10-22 12:04:19 +02:00
tools
Add place and route script
2024-10-22 15:20:39 +02:00
application_fpga.bin.sha256
Add yosys flags to optimize synthesis
2024-10-22 12:46:12 +02:00
config.vlt
Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal
2023-03-01 13:37:31 +01:00
firmware.bin.sha512
FPGA: Move RAM address and data scrambling into the RAM module.
2024-08-30 10:53:13 +02:00
Makefile
Add yosys flags to optimize synthesis
2024-10-22 12:46:12 +02:00