101 Commits

Author	SHA1	Message	Date
Joachim Strömbergson	c271b48a53	FPGA: Remove redundant clock cycle counter ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-19 15:48:24 +02:00
Joachim Strömbergson	ec77b15eb8	FPGA: Increase SPI speed ... - Change SPI clock from 16 CPU cyles/flank to one cycle/flank - Remove separate flank length wait states in the FSM Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-19 15:48:07 +02:00
Joachim Strömbergson	8ce07683f8	FPGA: SPI-master improvements ... - Changed FSM states to localparams - Added localparam for SPI clock divisor - Added internal signal for divisor reached - Improved comments to clarify code - Fixed some minor textual nits Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-19 11:51:44 +02:00
Joachim Strömbergson	bb4469ffda	FPGA: Ignore warnings about blocking assignment in clocked processes ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-17 15:37:13 +02:00
Joachim Strömbergson	5d0358dd2f	FPGA: Add labels for generate statements ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-17 15:37:13 +02:00
Joachim Strömbergson	6d9fc7db11	FPGA: Add core local Makefile for linting the PicoRV32 ... - Add more flags to catch the issues seen when linting the FPGA. - Store issues in separate file for viewing. Remove with make clean. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-17 15:27:47 +02:00
Joachim Strömbergson	f61d254fda	Adding testbench and simulation targets for the SPI master.	2024-06-11 15:28:29 +02:00
Joachim Strömbergson	3bc2453287	A construction of a minimal SPI master. ... - NOTE: This is an optional feature, not built by default. Not included in the tk1 for sale at Tillitis shop. - This makes it possible to interface the SPI flash onboard TKey. - To include the SPI master in the build, use `make application_fpga.bin YOSYS_FLAG=-DINCLUDE_SPI_MASTER`. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-11 15:28:29 +02:00
Joachim Strömbergson	09df7ae97f	FPGA: Fix linting of tk1 core ... Add simultion models of udi_rom and sb_rbga_drv to lint-top target. Add ignore statements in tb_sb_rgba_drv to silence Verilator on parameters and signals not used in the sim model. Use RGBLEDEN in simulation model Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-10 14:22:59 +02:00
Joachim Strömbergson	cadf8e9849	FPGA: Add sim model of udi_rom ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-06-07 12:06:40 +02:00
Joachim Strömbergson	e961f46e79	Update Verilog version to 2005 for linting ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-04-24 08:44:08 +02:00
Joachim Strömbergson	f655196af7	Clarify the functional description of the touch_sense core ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-04-22 16:03:08 +02:00
Michael Cardell Widerkrantz	3cf218469c	hw/tool: UDI/UDS storage ... Describe how the UDI and UDS are actually stored in the FPGA, how they are accessed, and how they are initialled by the patch_uds_udi.py script. Co-authored-by: Joachim Strömbergson <joachim@assured.se>	2024-04-03 11:27:00 +02:00
Joachim Strömbergson	de668a0244	Clean up code and silence warnings after linting ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-03-20 16:39:53 +01:00
Joachim Strömbergson	f364b523cf	Change UDS address to three bits to match input port connection 'addr' ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-03-20 16:39:53 +01:00
Joachim Strömbergson	bbde62d3f5	Add PINMISSING lint ignore for I1 and I2 SB_LUT4 cells ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-03-20 16:39:52 +01:00
Joachim Strömbergson	8731908cb1	Support incremental builds for the bitstream. ... By patching the UDS and UDI into an already built bitstream, it is now not necessary to rebuild the entire build flow when changing the UDS and the UDI. This lowers re-build times significantly. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-03-20 16:39:45 +01:00
Joachim Strömbergson	8784a24b33	Change cpu_monitor to security_monitor and to also check RAM ... Change name of cpu_monitor to security_monitor and increase its functionality to include RAM access violations. If addresses in RAM but outside of physical RAM is accessed in any way the security_monitor traps the CPU in the same way as it already did for execution violations.	2024-03-20 14:36:55 +01:00
Joachim Strömbergson	3fb6d66cf3	Add set-only register for the force_trap signal to ensure ... that the device must be reset to get out of trap. This change also breaks a critical path. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2024-03-20 14:36:55 +01:00
blaufish	cced6aec31	Explicity make uart_core.rx_data a wire (#140)	2023-08-16 10:43:04 +02:00
Joachim Strömbergson	17ddb1f84a	Minor fix of ackronyms in the README ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:29 +02:00
Joachim Strömbergson	3e75818879	Fix spelling of toolruns dir ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:29 +02:00
Joachim Strömbergson	5e34802d1c	Update readme with info on API, status, usage and performance ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:28 +02:00
Joachim Strömbergson	361381210e	Add an initial testcase. Hard to simulate entropy ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:28 +02:00
Joachim Strömbergson	a76fc19c65	Add Makefile, testbench and support module needed to build som target ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:28 +02:00
Joachim Strömbergson	a517552c85	Update README with info about the core functions ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:28 +02:00
Joachim Strömbergson	bc7dfea9c4	Add test9: EXE monitor control and detection ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:28 +02:00
Joachim Strömbergson	4644c79cbd	Adding test 8: GPIO test ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:28 +02:00
Joachim Strömbergson	394e437c91	Add test7: Control of LED RGB outputs. ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:27 +02:00
Joachim Strömbergson	480f4e3d45	Add test6: Test that RAM ASLR and SCRAMBLE registers can be set by fw ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:27 +02:00
Joachim Strömbergson	d70937c11b	Improved messaging from the testbench ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:27 +02:00
Joachim Strömbergson	59af60bdd5	Add test4: writing and reading blake2s entry point ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:27 +02:00
Joachim Strömbergson	dc2903a5b4	Update test3 to check that writing to CDI works when in fw mode ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:27 +02:00
Joachim Strömbergson	16a91bfdd5	Adding test 3: Reading out the CDI ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:27 +02:00
Joachim Strömbergson	1f47991ac2	Add test2: Read out UDI ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:27 +02:00
Joachim Strömbergson	6d9890d050	Add test1: Read out name and version ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:26 +02:00
Joachim Strömbergson	49eac9d101	Complete init of DUT and input, output display ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:26 +02:00
Joachim Strömbergson	1909833952	Add header with info and license ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:26 +02:00
Joachim Strömbergson	b1993742bb	Fix testbench buik including DUT instantiation ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:26 +02:00
Joachim Strömbergson	2fb61bba73	Add UDI used during simulation ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:26 +02:00
Joachim Strömbergson	cb2fd573b3	Add dummy LED macro driver module needed for simulation ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:26 +02:00
Joachim Strömbergson	61598f57e5	Add initial version of testbench annd Makfile for building sim target ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:26 +02:00
Joachim Strömbergson	97e3e25d98	Update the UART README with info about the core and its API ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:25 +02:00
Joachim Strömbergson	704d67c8ab	Add Makefile to build sim. Debug sim build ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:25 +02:00
Joachim Strömbergson	819b93deff	Complete testbench and update README with API info ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:25 +02:00
Joachim Strömbergson	bbff7576df	Fix markdown syntax for API listing ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:25 +02:00
Joachim Strömbergson	e6eaad87dc	Update README with info about the timer API ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:25 +02:00
Joachim Strömbergson	4c54b4b60b	Add info about the API in the README ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:25 +02:00
Joachim Strömbergson	18bb9b8599	Making the testbench self checking ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:25 +02:00
Joachim Strömbergson	1d2a71ec0c	Change file extension to markdown ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2023-07-04 09:04:24 +02:00