Support incremental builds for the bitstream.
By patching the UDS and UDI into an already built bitstream, it is now not necessary to rebuild the entire build flow when changing the UDS and the UDI. This lowers re-build times significantly. Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson
Michael Cardell Widerkrantz
parent
29fd8338a7
commit
8731908cb1
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@ -65,8 +65,10 @@ VERILOG_SRCS = \
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$(P)/core/timer/rtl/timer_core.v \
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$(P)/core/timer/rtl/timer.v \
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$(P)/core/uds/rtl/uds.v \
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$(P)/core/uds/rtl/uds_rom.v \
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$(P)/core/touch_sense/rtl/touch_sense.v \
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$(P)/core/tk1/rtl/tk1.v \
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$(P)/core/tk1/rtl/udi_rom.v \
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$(P)/core/uart/rtl/uart_core.v \
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$(P)/core/uart/rtl/uart_fifo.v \
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$(P)/core/uart/rtl/uart.v \
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@ -228,17 +230,18 @@ tb:
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# Main FPGA build flow.
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# Synthesis. Place & Route. Bitstream generation.
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#-------------------------------------------------------------------
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synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
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synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex
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$(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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-p 'synth_ice40 -dsp -top application_fpga -json $@; write_verilog -attr2comment synth.v' \
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$(filter %.v, $^)
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application_fpga.asc: synth.json $(P)/data/$(PIN_FILE)
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application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
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$(NEXTPNR_PATH)nextpnr-ice40 --ignore-loops --up5k --package sg48 --json $< \
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--pcf $(P)/data/$(PIN_FILE) --asc $@
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--pcf $(P)/data/$(PIN_FILE) --write $@
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application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex
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UDS_HEX="$(P)/data/uds.hex" UDI_HEX="$(P)/data/udi.hex" OUT_ASC=$@ $(NEXTPNR_PATH)nextpnr-ice40 --up5k --package sg48 --ignore-loops --json $< --run tools/personalize.py
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application_fpga.bin: application_fpga.asc bram_fw.hex firmware.hex
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$(ICESTORM_PATH)icebram -v bram_fw.hex firmware.hex < $< > $<.tmp
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@ -320,6 +323,7 @@ clean: clean_fw
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rm -f bram_fw.hex
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rm -f synth.{log,v,json} route.v application_fpga.{asc,bin,vcd} application_fpga_testfw.bin
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rm -f tb_application_fpga.vvp synth_tb.vvp route_tb.vvp
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rm -f application_fpga_par.json
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rm -f *.vcd
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rm -f lint_issues.txt
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rm -rf verilated
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@ -99,9 +99,6 @@ module tk1(
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reg [31 : 0] cdi_mem [0 : 7];
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reg cdi_mem_we;
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reg [31 : 0] udi_mem [0 : 1];
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initial $readmemh(`UDI_HEX, udi_mem);
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reg switch_app_reg;
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reg switch_app_we;
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@ -156,6 +153,7 @@ module tk1(
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reg [2 : 0] muxed_led;
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wire [31:0] udi_rdata;
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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@ -196,6 +194,12 @@ module tk1(
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/* verilator lint_on PINMISSING */
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udi_rom rom_i(
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.addr(address[0]),
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.data(udi_rdata)
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);
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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@ -500,7 +504,7 @@ module tk1(
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if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin
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if (!switch_app_reg) begin
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tmp_read_data = udi_mem[address[0]];
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tmp_read_data = udi_rdata;
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end
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end
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end
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@ -0,0 +1,35 @@
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//======================================================================
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//
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// udi_rom.v
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// ---------
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// UDI rom generated by instatiating named SB_LUT4 resources.
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// Note: This makes the design tech specicific.
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//
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//
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// Author: Claire Xiena Wolf.
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// Copyright (C) 2023 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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module udi_rom (
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input wire [0:0] addr,
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output wire [31:0] data
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);
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generate
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genvar ii;
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for (ii = 0; ii < 32; ii = ii + 1'b1) begin: luts
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(* udi_rom_idx=ii, keep *) SB_LUT4
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#(
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.LUT_INIT({2'h1})
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) lut_i (
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.I0(addr[0]),
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.O(data[ii])
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);
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end
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endgenerate
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endmodule
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//======================================================================
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// EOF udi_rom.v
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//======================================================================
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@ -36,9 +36,6 @@ module uds(
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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//----------------------------------------------------------------
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reg [31 : 0] uds_reg [0 : 7];
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initial $readmemh(`UDS_HEX, uds_reg);
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reg uds_rd_reg [0 : 7];
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reg uds_rd_we;
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@ -57,6 +54,17 @@ module uds(
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assign ready = tmp_ready;
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//----------------------------------------------------------------
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// uds rom instance.
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//----------------------------------------------------------------
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uds_rom rom_i(
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.addr(address),
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.re(uds_rd_we),
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.data(tmp_read_data)
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);
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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@ -85,7 +93,6 @@ module uds(
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always @*
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begin : api
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uds_rd_we = 1'h0;
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tmp_read_data = 32'h0;
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tmp_ready = 1'h0;
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if (cs) begin
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@ -94,14 +101,12 @@ module uds(
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if ((address >= ADDR_UDS_FIRST) && (address <= ADDR_UDS_LAST)) begin
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if (!fw_app_mode) begin
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if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
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tmp_read_data = uds_reg[address[2 : 0]];
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uds_rd_we = 1'h1;
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end
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end
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end
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end
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end
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endmodule // uds
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//======================================================================
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@ -0,0 +1,39 @@
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//======================================================================
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//
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// uds_rom.v
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// ---------
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// UDS rom. Generated by instantiating named SB_LUT4 resources.
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// Note: This makes the design technology specific.
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//
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//
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// Author: Claire Xenia Wolf
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// Copyright (C) 2023 - YosysHQ, Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module uds_rom(
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input wire [2:0] addr,
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input wire re,
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output wire [31:0] data
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);
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generate
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genvar ii;
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for (ii = 0; ii < 32; ii = ii + 1'b1) begin: luts
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(* uds_rom_idx=ii, keep *) SB_LUT4
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#(
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.LUT_INIT({8'ha6 ^ ii[7:0], 8'h00})
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) lut_i (
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.I0(addr[0]), .I1(addr[1]), .I2(addr[2]), .I3(re),
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.O(data[ii])
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);
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end
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endgenerate
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endmodule // uds_rom
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//======================================================================
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// EOF uds_rom.v
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//======================================================================
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@ -0,0 +1,63 @@
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# -*- coding: utf-8 -*-
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#=======================================================================
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#
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# personalize.py
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# --------------
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# Python program that patches the UDS and UDI implemented using
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# named LUT4 instances to have unique initial values, not the generic
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# values used during synthesis, p&r and mapping. This allows us to
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# generate device unique bitstreams without running the complete flow.
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#
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#
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# Copyright (C) 2023 Tillitis AB
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# Written by Myrtle Shah <gatecat@ds0.me>
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#=======================================================================
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import os
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def parse_hex(file, length):
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data = []
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with open(file, "r") as f:
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for line in f:
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l = line.strip()
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if len(l) > 0:
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data.append(int(l, 16))
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assert len(data) == length, len(data)
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return data
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def rewrite_lut(lut, idx, data, has_re=False):
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# each LUT provides one bit per 32-bit word out of 64/256 bits total
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new_init = 0
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for i, word in enumerate(data):
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if (word >> idx) & 0x1:
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# repeat so inputs above address have a don't care value
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repeat = (16 // len(data))
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for k in range(repeat):
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# UDS also has a read enable
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# LUT output is zero if this isn't asserted
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if has_re and k < (repeat // 2):
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continue
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new_init |= (1 << (k * len(data) + i))
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lut.setParam("LUT_INIT", f"{new_init:016b}")
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uds = parse_hex(os.environ["UDS_HEX"], 8)
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udi = parse_hex(os.environ["UDI_HEX"], 2)
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uds_lut_count = 0
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udi_lut_count = 0
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for cell_name, cell in ctx.cells:
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if "uds_rom_idx" in cell.attrs:
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index = int(cell.attrs["uds_rom_idx"], 2)
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rewrite_lut(cell, index, uds, True)
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uds_lut_count += 1
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if "udi_rom_idx" in cell.attrs:
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index = int(cell.attrs["udi_rom_idx"], 2)
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rewrite_lut(cell, index, udi, False)
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udi_lut_count += 1
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assert uds_lut_count == 32, uds_lut_count
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assert udi_lut_count == 32, udi_lut_count
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write_bitstream(ctx, os.environ["OUT_ASC"])
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