Explicity make uart_core.rx_data a wire (#140)

2024-09-27 20:05:46 +00:00 · 2023-08-16 10:43:04 +02:00 · 2023-08-16 10:43:04 +02:00 · cced6aec31
commit cced6aec31
parent 1ab36c7c83
1 changed files with 1 additions and 1 deletions
--- a/hw/application_fpga/core/uart/rtl/uart_core.v
+++ b/hw/application_fpga/core/uart/rtl/uart_core.v
@ -61,7 +61,7 @@ module uart_core(

                 // Internal receive interface.
                 output wire         rxd_syn,
-                 output [7 : 0]      rxd_data,
+                 output wire [7 : 0] rxd_data,
                 input wire          rxd_ack,

                 // Internal transmit interface.