Joachim Strömbergson 09df7ae97f FPGA: Fix linting of tk1 core ... Add simultion models of udi_rom and sb_rbga_drv to lint-top target. Add ignore statements in tb_sb_rgba_drv to silence Verilator on parameters and signals not used in the sim model. Use RGBLEDEN in simulation model Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-06-10 14:22:59 +02:00
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picorv32	Squashed commit of the following:	2022-10-06 13:23:30 +02:00
timer	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
tk1	FPGA: Fix linting of tk1 core	2024-06-10 14:22:59 +02:00
touch_sense	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
trng	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uart	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uds	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00