Joachim Strömbergson ec77b15eb8 FPGA: Increase SPI speed ... - Change SPI clock from 16 CPU cyles/flank to one cycle/flank - Remove separate flank length wait states in the FSM Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-06-19 15:48:07 +02:00
..
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
timer	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
tk1	FPGA: Increase SPI speed	2024-06-19 15:48:07 +02:00
touch_sense	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
trng	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uart	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uds	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00