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FPGA: Add sim model of udi_rom

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-06-03 15:07:01 +02:00 committed by dehanj
parent 0454e023cd
commit cadf8e9849
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2 changed files with 37 additions and 1 deletions
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36
hw/application_fpga/core/tk1/tb/udi_rom_sim.v Normal file
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@ -0,0 +1,36 @@
//======================================================================
//
// udi_rom_sim.v
// ---------
// Simulation version of the UDI ROM.
//
//
// Author: Joachim Strömbergson.
// Copyright (C) 2023 - Tillitis AB
// SPDX-License-Identifier: GPL-2.0-only
//
//======================================================================
module udi_rom (
input wire [0:0] addr,
output wire [31:0] data
);
reg [31 : 0] tmp_data;
assign data = tmp_data;
always @*
begin : addr_mux
if (addr) begin
tmp_data = 32'h04050607;
end
else begin
tmp_data = 32'h00010203;
end
end
endmodule // udi_rom
//======================================================================
// EOF udi_rom_sim.v
//======================================================================

2
hw/application_fpga/core/tk1/toolruns/Makefile
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@ -12,7 +12,7 @@
#===================================================================
TOP_SRC=../rtl/tk1.v
TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv.v
TB_TOP_SRC =../tb/tb_tk1.v ../tb/sb_rgba_drv.v ../tb/udi_rom_sim.v
CC = iverilog
CC_FLAGS = -Wall