Daniel Jobson
5b49d80891
tb: make timer core testbench selftesting
...
- Compare against an expected result and count errors
- Exit with the right error code
- Clean up the output
2024-11-27 08:10:15 +01:00
Daniel Jobson
c735c6fdde
tb: make tb_timer.v selftesting
...
- Compare against an expected result and count errors
- Exit with the right error code
- Lower write_word() to 1 clk cycle instead of two. It only requires one
clock cycle to write, otherwise if it is two one have to compensate for it
in the tests since we are counting cycles.
2024-11-27 08:10:15 +01:00
Daniel Jobson
6bdedf4f86
Fix bug in timer core, where it misses clock cycles
...
Remove redundant timer state. This fixes a bug where the timer misses a
clock cycle every time the prescaler counter reaches 1. This means if
one uses a large prescaler, like 18E6, it is barely noticeable, but if
one have a low prescaler and a high timer value it becomes significant.
This also yields the running_* registers redundant, which are removed.
Add clarity to the readme.
Update the timer to default to values of one, for prescaler and timer
count.
2024-11-27 08:10:15 +01:00
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code
2024-10-22 12:04:19 +02:00
Joachim Strömbergson
e961f46e79
Update Verilog version to 2005 for linting
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-04-24 08:44:08 +02:00
Joachim Strömbergson
e6eaad87dc
Update README with info about the timer API
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:25 +02:00
Joachim Strömbergson
9d188a2f7f
Add more info about how the timer works
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:24 +02:00
Joachim Strömbergson
7c9dfaf45a
Add testcase for the timer top level wrapper and clean up the tb
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:24 +02:00
Joachim Strömbergson
c185849ae4
Minor cleanup of README, testbench and Makefile
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:24 +02:00
Joachim Strömbergson
6137b88fe0
Add separate start, stop bits and running status bit in API
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-30 15:48:57 +01:00
Joachim Strömbergson
f020495695
Cleanup of tb for timer core
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-20 10:14:44 +01:00
Joachim Strömbergson
ddd969870e
Count from init values to one, not zero
2022-10-18 11:06:40 +02:00
Joachim Strömbergson
f6046d55a9
Change ADDR_CTRL to be a pulsed start_stop signal
2022-10-14 08:50:30 +02:00
Joachim Strömbergson
c3f7c5fb06
Ignore the prescaler if prescaler init value is zero
2022-10-13 16:24:03 +02:00
Joachim Strömbergson
2be934ee22
Restore start and stop bits, but clarify in documenation
2022-10-13 16:10:08 +02:00
Joachim Strömbergson
00d180d34e
Change to a single run bit and update access control
2022-10-13 14:58:39 +02:00
Joachim Strömbergson
82a64f2b2c
Remove DONE state that added one extra final cycle
2022-10-12 10:06:41 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores
...
timer
touch_sense
figaro
uart
uds
2022-10-11 09:50:45 +02:00
Joachim Strömbergson
c90771fe19
Remove API access to current prescaler value
2022-10-06 15:56:13 +02:00
Joachim Strömbergson
715de60f4a
Make initial public release
2022-09-19 08:51:11 +02:00
