tillitis-key/hw/application_fpga/core/timer
2022-10-14 08:50:30 +02:00
..
rtl Change ADDR_CTRL to be a pulsed start_stop signal 2022-10-14 08:50:30 +02:00
tb Remove API access to current prescaler value 2022-10-06 15:56:13 +02:00
toolruns Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

timer

A simple timer with prescaler written in Verilog.

Introduction

This core implements a simple timer with a prescaler. The purpose of the prescaler is to more easily time durations rather than cycles. If for example setting the timer to the clock frequency, the timer can cound seconds.