mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00

History

Joachim Strömbergson c3f7c5fb06 Ignore the prescaler if prescaler init value is zero		2022-10-13 16:24:03 +02:00
..
rtl	Ignore the prescaler if prescaler init value is zero	2022-10-13 16:24:03 +02:00
tb	Remove API access to current prescaler value	2022-10-06 15:56:13 +02:00
toolruns	Make initial public release	2022-09-19 08:51:11 +02:00
README.md	Make initial public release	2022-09-19 08:51:11 +02:00

README.md

timer

A simple timer with prescaler written in Verilog.

Introduction

This core implements a simple timer with a prescaler. The purpose of the prescaler is to more easily time durations rather than cycles. If for example setting the timer to the clock frequency, the timer can cound seconds.