Minor cleanup of README, testbench and Makefile

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

hw/application_fpga/core/timer/README.md

@@ -1,5 +1,13 @@
 # timer
-A simple timer with prescaler written in Verilog.
+A simple timer with prescaler.
 
 ## Introduction
-This core implements a simple timer with a prescaler. The purpose of the prescaler is to more easily time durations rather than cycles. If for example setting the timer to the clock frequency, the timer can cound seconds.
+This core implements a simple timer with a prescaler. The prescaler
+allows measurement of time durations rather than cycles. If for
+example setting the prescaler to the clock frequency in Hertz, the
+timer will count seconds.
+
+
+## Details
+The timer counter and the prescaler counter are both 32 bits.
+When enabled the counter counts down one integer value per cycle.

hw/application_fpga/core/timer/tb/tb_timer_core.v

@@ -222,7 +222,7 @@ module tb_timer_core();
   //----------------------------------------------------------------
   initial
     begin : timer_core_test
-      $display("--- Simulation of TIMER core started.");
+      $display("--- Simulation of timer core started.");
       $display("");
 
       init_sim();

hw/application_fpga/core/timer/toolruns/Makefile

@@ -57,7 +57,7 @@ clean:
 
 
 help:
-	@echo "Build system for simulation of Prince core"
+	@echo "Build system for simulation of timer core"
 	@echo ""
 	@echo "Supported targets:"
 	@echo "------------------"