Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00
Code Issues Packages Projects Releases Wiki Activity
c90771fe19
tillitis-key/hw/application_fpga/core/timer
History
Joachim Strömbergson c90771fe19
Remove API access to current prescaler value
2022-10-06 15:56:13 +02:00
..
rtl Remove API access to current prescaler value 2022-10-06 15:56:13 +02:00
tb Remove API access to current prescaler value 2022-10-06 15:56:13 +02:00
toolruns Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

README.md

timer

A simple timer with prescaler written in Verilog.

Introduction

This core implements a simple timer with a prescaler. The purpose of the prescaler is to more easily time durations rather than cycles. If for example setting the timer to the clock frequency, the timer can cound seconds.