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6137b88fe0
tillitis-key/hw/application_fpga/core/timer
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Joachim Strömbergson 6137b88fe0 Add separate start, stop bits and running status bit in API 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-30 15:48:57 +01:00
..
rtl Add separate start, stop bits and running status bit in API 2023-01-30 15:48:57 +01:00
tb Add separate start, stop bits and running status bit in API 2023-01-30 15:48:57 +01:00
toolruns Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

README.md

timer

A simple timer with prescaler written in Verilog.

Introduction

This core implements a simple timer with a prescaler. The purpose of the prescaler is to more easily time durations rather than cycles. If for example setting the timer to the clock frequency, the timer can cound seconds.