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Change ADDR_CTRL to be a pulsed start_stop signal

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Joachim Strömbergson 2022-10-14 08:50:30 +02:00
parent c3f7c5fb06
commit f6046d55a9
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GPG Key ID: 865B8A548EA61679
3 changed files with 17 additions and 30 deletions
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36
hw/application_fpga/core/timer/rtl/timer.v
View File

@ -31,8 +31,6 @@ module timer(
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_CTRL = 8'h08;
localparam CTRL_START_BIT = 0;
localparam CTRL_STOP_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
@ -50,11 +48,8 @@ module timer(
reg [31 : 0] timer_reg;
reg timer_we;
reg start_reg;
reg start_new;
reg stop_reg;
reg stop_new;
reg start_stop_reg;
reg start_stop_new;
//----------------------------------------------------------------
@ -83,8 +78,7 @@ module timer(
.prescaler_init(prescaler_reg),
.timer_init(timer_reg),
.start(start_reg),
.stop(stop_reg),
.start_stop(start_stop_reg),
.curr_timer(core_curr_timer),
.ready(core_ready)
@ -97,14 +91,12 @@ module timer(
always @ (posedge clk)
begin : reg_update
if (!reset_n) begin
start_reg <= 1'h0;
stop_reg <= 1'h0;
prescaler_reg <= 32'h0;
timer_reg <= 32'h0;
start_stop_reg <= 1'h0;
prescaler_reg <= 32'h0;
timer_reg <= 32'h0;
end
else begin
start_reg <= start_new;
stop_reg <= stop_new;
start_stop_reg <= start_stop_new;
if (prescaler_we) begin
prescaler_reg <= write_data;
@ -124,20 +116,18 @@ module timer(
//----------------------------------------------------------------
always @*
begin : api
start_new = 1'h0;
stop_new = 1'h0;
prescaler_we = 1'h0;
timer_we = 1'h0;
tmp_read_data = 32'h0;
tmp_ready = 1'h0;
start_stop_new = 1'h0;
prescaler_we = 1'h0;
timer_we = 1'h0;
tmp_read_data = 32'h0;
tmp_ready = 1'h0;
if (cs) begin
tmp_ready = 1'h1;
if (we) begin
if (address == ADDR_CTRL) begin
start_new = write_data[CTRL_START_BIT];
stop_new = write_data[CTRL_STOP_BIT];
start_stop_new = 1'h1;
end
if (core_ready) begin

9
hw/application_fpga/core/timer/rtl/timer_core.v
View File

@ -19,8 +19,7 @@ module timer_core(
input wire [31 : 0] prescaler_init,
input wire [31 : 0] timer_init,
input wire start,
input wire stop,
input wire start_stop,
output wire [31 : 0] curr_timer,
output wire ready
@ -153,7 +152,7 @@ module timer_core(
case (core_ctrl_reg)
CTRL_IDLE: begin
if (start)
if (start_stop)
begin
ready_new = 1'h0;
ready_we = 1'h1;
@ -171,7 +170,7 @@ module timer_core(
CTRL_PRESCALER: begin
if (stop) begin
if (start_stop) begin
ready_new = 1'h1;
ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE;
@ -190,7 +189,7 @@ module timer_core(
CTRL_TIMER: begin
if (stop) begin
if (start_stop) begin
ready_new = 1'h1;
ready_we = 1'h1;
core_ctrl_new = CTRL_IDLE;

2
hw/application_fpga/fw/mta1_mkdf_mem.h
View File

@ -43,8 +43,6 @@ enum {
MTA1_MKDF_MMIO_TRNG_ENTROPY = MTA1_MKDF_MMIO_TRNG_BASE | 0x80,
MTA1_MKDF_MMIO_TIMER_CTRL = MTA1_MKDF_MMIO_TIMER_BASE | 0x20,
MTA1_MKDF_MMIO_TIMER_CTRL_START_BIT = 0,
MTA1_MKDF_MMIO_TIMER_CTRL_STOP_BIT = 1,
MTA1_MKDF_MMIO_TIMER_STATUS = MTA1_MKDF_MMIO_TIMER_BASE | 0x24,
MTA1_MKDF_MMIO_TIMER_STATUS_READY_BIT = 0,
MTA1_MKDF_MMIO_TIMER_PRESCALER = MTA1_MKDF_MMIO_TIMER_BASE | 0x28,