Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-04-15 04:53:08 -04:00
Code Issues Packages Projects Releases Wiki Activity

tb: make timer core testbench selftesting

Browse Source 
- Compare against an expected result and count errors
- Exit with the right error code
- Clean up the output
This commit is contained in:
Daniel Jobson 2024-11-22 13:40:43 +01:00
parent c735c6fdde
commit 5b49d80891
No known key found for this signature in database
GPG Key ID: 3707A9DBF4BB8F1A
1 changed files with 65 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

81
hw/application_fpga/core/timer/tb/tb_timer_core.v
View File

@ -122,14 +122,18 @@ module tb_timer_core ();
//----------------------------------------------------------------
task reset_dut;
begin
$display("--- DUT before reset:");
dump_dut_state();
if (tb_monitor) begin
$display("--- DUT before reset:");
dump_dut_state();
end
$display("--- Toggling reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("--- DUT after reset:");
dump_dut_state();
if (tb_monitor) begin
$display("--- DUT after reset:");
dump_dut_state();
end
end
endtask // reset_dut
@ -187,26 +191,67 @@ module tb_timer_core ();
// Check so the clock cycles passed adds up to timer * prescaler.
//----------------------------------------------------------------
task test1;
begin
tc_ctr = tc_ctr + 1;
tb_monitor = 1;
begin : test1
reg [31 : 0] test1_cycle_ctr_start;
reg [31 : 0] test1_counted_num_cycles;
reg [31 : 0] test1_expected_num_cycles;
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test1: Run timer to set value started.");
$display("--- test1: prescaler: 6, timer: 9. Should take 6*9 = 54 cycles..");
$display("--- test1 started.");
dump_dut_state();
tb_prescaler_init = 32'h6;
tb_timer_init = 32'h9;
tb_timer_init = 32'h9;
test1_expected_num_cycles = tb_prescaler_init * tb_timer_init;
#(CLK_PERIOD);
tb_start = 1'h1;
#(CLK_PERIOD);
test1_cycle_ctr_start = cycle_ctr;
tb_start = 1'h0;
wait_done();
#(CLK_PERIOD);
tb_monitor = 0;
$display("--- test1 completed.");
while (tb_running) begin
#(CLK_PERIOD);
end
test1_counted_num_cycles = cycle_ctr - test1_cycle_ctr_start;
if (test1_counted_num_cycles == test1_expected_num_cycles) begin
$display("--- test1: Correct number of cycles counted: %0d", test1_counted_num_cycles);
end
else begin
$display("--- test1: Error, expected %0d cycles, counted cycles: %0d",
test1_expected_num_cycles, test1_counted_num_cycles);
error_ctr = error_ctr + 1;
end
$display("--- test1: Completed.");
$display("");
end
endtask // test1
//----------------------------------------------------------------
// exit_with_error_code()
//
// Exit with the right error code
//----------------------------------------------------------------
task exit_with_error_code;
begin
if (error_ctr == 0) begin
$finish(0);
end
else begin
$fatal(1);
end
end
endtask // exit_with_error_code
//----------------------------------------------------------------
// timer_core_test
@ -214,7 +259,9 @@ module tb_timer_core ();
// Test vectors from:
//----------------------------------------------------------------
initial begin : timer_core_test
$display("--- Simulation of timer core started.");
$display("");
$display(" -= Simulation of timer core started =-");
$display(" ===============================");
$display("");
init_sim();
@ -223,8 +270,10 @@ module tb_timer_core ();
test1();
$display("");
$display("--- Simulation of timer core completed.");
$finish;
$display(" -= Simulation of timer core completed =-");
$display(" ===============================");
$display("");
exit_with_error_code();
end // timer_core_test
endmodule // tb_timer_core