Joachim Strömbergson
fbd1620891
fpga: Add stateful access control
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Add access stateful control register that toggles if access to a
resources is granted based on if code is excuted from ROM or RAM.
The register is used to enable or block access to SPI but
potentially other HW resources.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-07-09 16:00:04 +02:00
Joachim Strömbergson
3bc2453287
A construction of a minimal SPI master.
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- NOTE: This is an optional feature, not built by default. Not included
in the tk1 for sale at Tillitis shop.
- This makes it possible to interface the SPI flash onboard TKey.
- To include the SPI master in the build, use `make application_fpga.bin
YOSYS_FLAG=-DINCLUDE_SPI_MASTER`.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-06-11 15:28:29 +02:00
Joachim Strömbergson
de668a0244
Clean up code and silence warnings after linting
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-03-20 16:39:53 +01:00
Joachim Strömbergson
f364b523cf
Change UDS address to three bits to match input port connection 'addr'
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-03-20 16:39:53 +01:00
Joachim Strömbergson
4c3e210a00
Only set ram_we to cpu_wstrb in RAM_PREFIX
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-03-20 14:36:55 +01:00
Joachim Strömbergson
e48c0fc7d9
Implement cs0 and cs1 as logic equations, not muxes
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-03-20 14:36:55 +01:00
blaufish
426b56ebf5
Verilog 2001 rule; use wires for assignments, not registers. ( #139 )
2023-08-16 10:44:18 +02:00
Joachim Strömbergson
b9c415f5d6
bank1 access should also be disabled by default.
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-13 12:43:07 +01:00
Daniel Lublin
5f4f5c6584
Correct for new fw-ram size
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Signed-off-by: Daniel Lublin <daniel@lublin.se>
2023-03-08 12:34:34 +01:00
Joachim Strömbergson
a63ba8eb13
Double the size of the fw_ram to 2 kByte
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-08 11:20:38 +01:00
Joachim Strömbergson
d075cc72c3
Manually merged changes for scrambling
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-07 10:42:59 +01:00
Joachim Strömbergson
74fd7e3001
Fix spelling nits
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-07 08:16:42 +01:00
Joachim Strömbergson
7612d00ccf
Feed CPU illegal instruction to trigger trap
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 15:41:55 +01:00
Joachim Strömbergson
8ba97e16f3
Move force_jump function to top level mem system
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 15:41:54 +01:00
Joachim Strömbergson
86ea45e10a
Add CPU execution monitor
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 15:41:53 +01:00
Joachim Strömbergson
d335dd708a
Add HW to detect trap in cpu and signal using the LEDs
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-06 11:32:38 +01:00
Joachim Strömbergson
317561ad32
Remove options that are the same as the default values
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-02-27 10:22:04 +01:00
Joachim Strömbergson
ab03ebd12c
Improve wording ans size info in header
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-30 13:19:01 +01:00
Joachim Strömbergson
cc464e5be2
The memory is 256 x 32 bits, not 512 x 32 bits
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-30 13:00:43 +01:00
Joachim Strömbergson
2fa1ffb8e7
Disable HW support in CPU for DIV
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2022-11-28 16:15:01 +01:00
Joachim Strömbergson
159b20fa4e
Zero extend the address to match SB_RAM4K ports
2022-11-09 15:05:03 +01:00
Daniel Lublin
4b4f014d38
Rename to TK1
2022-10-26 09:20:02 +02:00
Daniel Lublin
ecc2923387
Explain how we attain 18 MHz
2022-10-21 14:33:03 +02:00
Joachim Strömbergson
51a22dc32c
Merge branch 'fw_ram'
2022-10-13 13:16:53 +02:00
Joachim Strömbergson
8e493b6322
Debug fw_ram and add fw_app_mode access control
2022-10-13 13:14:10 +02:00
Joachim Strömbergson
cbf1104fed
Write whole byte, not nybbles
2022-10-11 17:05:21 +02:00
Joachim Strömbergson
a51619e5b7
Add fw_ram module
2022-10-11 16:58:26 +02:00
Joachim Strömbergson
24cf80af32
Remove redundant spram module
2022-10-11 13:27:57 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG
2022-10-11 13:17:04 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
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Silence lint on intentional combinatinal loops
Use better instance names, and a single lint pragma for all macros
Remove unused pointer update signals
Silence lint on wires where not all bits are used
Change fw_app_mode to be an input port to allow access control
Remove redundant, unused wire mem_busy
Add lint pragma to ignore debug register only enabled by a define
Remove clk and reset_n ports from the ROM
Adding note and lint pragma for rom address width
Fix incorrect register widths in uart_core
Assign all 16 bits in LUT config
Silence lint warnings on macro instances
Correct bit extraction for core addresses to be eight bits wide
Correct the bit width of cdi_mem_we wire
Add specific output file for logging lint issues
Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Joachim Strömbergson
1aa2d7bd95
Merge branch 'pll'
2022-09-30 10:06:48 +02:00
Joachim Strömbergson
f09ff87f9e
Support DIV instructions and catch illegal instructions
2022-09-28 10:29:00 +02:00
Joachim Strömbergson
90a57c4948
Use PLL and global buffer to increas clock speed
2022-09-27 16:41:38 +02:00
Joachim Strömbergson
3110d1218d
Silence lint re missing pins on cell instances
2022-09-19 10:35:49 +02:00
Joachim Strömbergson
715de60f4a
Make initial public release
2022-09-19 08:51:11 +02:00
