Daniel Lublin ecc2923387

Explain how we attain 18 MHz

2022-10-21 14:33:03 +02:00

..

application_fpga.v

Add fw_ram module

2022-10-11 16:58:26 +02:00

clk_reset_gen.v

Explain how we attain 18 MHz

2022-10-21 14:33:03 +02:00

fw_ram.v

Debug fw_ram and add fw_app_mode access control

2022-10-13 13:14:10 +02:00

ram.v

Make initial public release

2022-09-19 08:51:11 +02:00

rom.v

Squashed commit of the following:

2022-10-06 13:23:30 +02:00