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Support DIV instructions and catch illegal instructions
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@ -165,10 +165,10 @@ module application_fpga(
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.TWO_STAGE_SHIFT(0),
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.TWO_CYCLE_ALU(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0),
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.CATCH_ILLINSN(1),
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.COMPRESSED_ISA(1),
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.ENABLE_FAST_MUL(1),
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.ENABLE_DIV(0),
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.ENABLE_DIV(1),
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.BARREL_SHIFTER(1)
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) cpu(
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.clk(clk),
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