Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-10-01 01:45:38 -04:00
Code Issues Packages Projects Releases Wiki Activity

Verilog 2001 rule; use wires for assignments, not registers. (#139)

Browse Source
This commit is contained in:
blaufish 2023-08-16 10:44:18 +02:00 committed by GitHub
parent cced6aec31
commit 426b56ebf5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/application_fpga/rtl/fw_ram.v
View File

@ -35,7 +35,7 @@ module fw_ram(
reg [31 : 0] mem_read_data0;
reg [31 : 0] mem_read_data1;
reg ready_reg;
reg fw_app_cs;
wire fw_app_cs;
reg bank0;
reg bank1;