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Implement cs0 and cs1 as logic equations, not muxes 

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-03-18 14:41:52 +01:00 committed by Michael Cardell Widerkrantz
parent 0590445f3d
commit e48c0fc7d9
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GPG Key ID: D3DB3DDF57E704E5
1 changed files with 2 additions and 4 deletions
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6
hw/application_fpga/rtl/ram.v
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@ -125,14 +125,12 @@ module ram(
//----------------------------------------------------------------
always @*
begin : mem_mux
cs0 = 1'h0;
cs1 = 1'h0;
cs0 = ~address[14] & cs;
cs1 = address[14] & cs;
if (address[14]) begin
cs1 = cs;
muxed_read_data = read_data1;
end else begin
cs0 = cs;
muxed_read_data = read_data0;
end
end