Joachim Strömbergson f364b523cf Change UDS address to three bits to match input port connection 'addr' ... Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-03-20 16:39:53 +01:00
..
application_fpga.v	Change UDS address to three bits to match input port connection 'addr'	2024-03-20 16:39:53 +01:00
clk_reset_gen.v	Explain how we attain 18 MHz	2022-10-21 14:33:03 +02:00
fw_ram.v	Verilog 2001 rule; use wires for assignments, not registers. (#139)	2023-08-16 10:44:18 +02:00
ram.v	Implement cs0 and cs1 as logic equations, not muxes	2024-03-20 14:36:55 +01:00
rom.v	Move force_jump function to top level mem system	2023-03-06 15:41:54 +01:00