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Double the size of the fw_ram to 2 kByte

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-03-08 11:20:38 +01:00
parent 0a31685dc0
commit a63ba8eb13
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GPG Key ID: 865B8A548EA61679
2 changed files with 68 additions and 29 deletions
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4
hw/application_fpga/rtl/application_fpga.v
View File

@ -132,7 +132,7 @@ module application_fpga(
reg fw_ram_cs;
/* verilator lint_on UNOPTFLAT */
reg [3 : 0] fw_ram_we;
reg [7 : 0] fw_ram_address;
reg [8 : 0] fw_ram_address;
reg [31 : 0] fw_ram_write_data;
wire [31 : 0] fw_ram_read_data;
wire fw_ram_ready;
@ -390,7 +390,7 @@ module application_fpga(
fw_ram_cs = 1'h0;
fw_ram_we = cpu_wstrb;
fw_ram_address = cpu_addr[9 : 2];
fw_ram_address = cpu_addr[10 : 2];
fw_ram_write_data = cpu_wdata;
trng_cs = 1'h0;

93
hw/application_fpga/rtl/fw_ram.v
View File

@ -21,7 +21,7 @@ module fw_ram(
input wire cs,
input wire [3 : 0] we,
input wire [7 : 0] address,
input wire [8 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready
@ -32,9 +32,12 @@ module fw_ram(
// Registers and wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg [31 : 0] mem_read_data;
reg [31 : 0] mem_read_data0;
reg [31 : 0] mem_read_data1;
reg ready_reg;
reg fw_app_cs;
reg bank0;
reg bank1;
//----------------------------------------------------------------
@ -48,36 +51,63 @@ module fw_ram(
//----------------------------------------------------------------
// Block RAM instances.
//----------------------------------------------------------------
SB_RAM40_4K fw_ram0(
.RDATA(mem_read_data[15 : 0]),
.RADDR({3'h0, address}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs),
.WADDR({3'h0, address}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we && fw_app_cs)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
SB_RAM40_4K fw_ram0_0(
.RDATA(mem_read_data0[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
SB_RAM40_4K fw_ram0_1(
.RDATA(mem_read_data0[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank0),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we & fw_app_cs & bank0)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);
SB_RAM40_4K fw_ram1(
.RDATA(mem_read_data[31 : 16]),
.RADDR({3'h0, address}),
SB_RAM40_4K fw_ram1_0(
.RDATA(mem_read_data1[15 : 0]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[15 : 0]),
.WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[1]}}, {8{~we[0]}}})
);
SB_RAM40_4K fw_ram1_1(
.RDATA(mem_read_data1[31 : 16]),
.RADDR({3'h0, address[7 : 0]}),
.RCLK(clk),
.RCLKE(1'h1),
.RE(fw_app_cs),
.WADDR({3'h0, address}),
.RE(fw_app_cs & bank1),
.WADDR({3'h0, address[7 : 0]}),
.WCLK(clk),
.WCLKE(1'h1),
.WDATA(write_data[31 : 16]),
.WE((|we && fw_app_cs)),
.WE((|we & fw_app_cs & bank1)),
.MASK({{8{~we[3]}}, {8{~we[2]}}})
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
@ -93,14 +123,23 @@ module fw_ram(
//----------------------------------------------------------------
// read_mux
// rw_mux
//----------------------------------------------------------------
always @*
begin : read_mux;
begin : rw_mux;
bank0 = 1'h0;
bank1 = 1'h1;
tmp_read_data = 32'h0;
if (fw_app_cs) begin
tmp_read_data = mem_read_data;
end else begin
tmp_read_data = 32'h0;
if (address[8]) begin
bank1 = 1'h1;
tmp_read_data = mem_read_data1;
end
else begin
bank0 = 1'h1;
tmp_read_data = mem_read_data0;
end
end
end