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Silence lint re missing pins on cell instances

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Joachim Strömbergson 2022-09-19 10:35:49 +02:00
parent 69fc33c524
commit 3110d1218d
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GPG Key ID: 865B8A548EA61679
3 changed files with 6 additions and 0 deletions
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2
hw/application_fpga/core/trng/rtl/firo.v
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@ -32,6 +32,7 @@ module firo(
//---------------------------------------------------------------
// Combinational loop inverters.
//---------------------------------------------------------------
/* verilator lint_off PINMISSING */
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv1 (.I0(f[0]), .O(f[1]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv2 (.I0(f[1]), .O(f[2]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv3 (.I0(f[2]), .O(f[3]));
@ -42,6 +43,7 @@ module firo(
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv8 (.I0(f[7]), .O(f[8]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv9 (.I0(f[8]), .O(f[9]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv10 (.I0(f[9]), .O(f[10]));
/* verilator lint_on PINMISSING */
//---------------------------------------------------------------

2
hw/application_fpga/core/trng/rtl/garo.v
View File

@ -33,6 +33,7 @@ module garo(
//---------------------------------------------------------------
// Combinational loop inverters.
//---------------------------------------------------------------
/* verilator lint_off PINMISSING */
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv1 (.I0(g[0]), .O(gp[0]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv2 (.I0(g[1]), .O(gp[1]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv3 (.I0(g[2]), .O(gp[2]));
@ -45,6 +46,7 @@ module garo(
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv10 (.I0(g[9]), .O(gp[9]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv11 (.I0(g[10]), .O(gp[10]));
(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv12 (.I0(g[11]), .O(gp[11]));
/* verilator lint_on PINMISSING */
//---------------------------------------------------------------

2
hw/application_fpga/rtl/application_fpga.v
View File

@ -149,8 +149,10 @@ module application_fpga(
//----------------------------------------------------------------
// Use the FPGA internal High Frequency OSCillator as clock source.
// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
/* verilator lint_off PINMISSING */
SB_HFOSC #(.CLKHF_DIV("0b10")
) u_hfosc (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(clk));
/* verilator lint_on PINMISSING */
reset_gen #(.RESET_CYCLES(200))