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Explain how we attain 18 MHz
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@ -55,6 +55,16 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
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// Use a PLL to generate a new clock frequency based on the HFOSC clock.
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//
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// Given FEEDBACK_PATH=="SIMPLE", clock calculation according to 3.5.2 in
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// FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf
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// https://www.latticesemi.com/view_document?document_id=47778 follows:
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//
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// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
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//
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// Given the 12 MHz HFOSC clock set above, we get a final 18 MHz:
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//
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// (12000000 * (47 + 1)) / (2^5 * (0 + 1)) = 18000000
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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