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Explain how we attain 18 MHz

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Daniel Lublin 2022-10-21 14:33:03 +02:00
parent 675fa1087f
commit ecc2923387
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hw/application_fpga/rtl/clk_reset_gen.v
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@ -55,6 +55,16 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
// Use a PLL to generate a new clock frequency based on the HFOSC clock.
//
// Given FEEDBACK_PATH=="SIMPLE", clock calculation according to 3.5.2 in
// FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf
// https://www.latticesemi.com/view_document?document_id=47778 follows:
//
// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
//
// Given the 12 MHz HFOSC clock set above, we get a final 18 MHz:
//
// (12000000 * (47 + 1)) / (2^5 * (0 + 1)) = 18000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0