Joachim Strömbergson
de4db95bb0
(fpga) Fix counting, add make test case self testing.
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Fix so that the timer counts the correct number of cycles
(again).
Make testbench self-testing.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-15 11:29:30 +02:00
Joachim Strömbergson
041559f19a
(fpga) Integrate free running support in API
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Add support in the Timer API to enable the free runing mode.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-15 08:43:25 +02:00
Joachim Strömbergson
9c465cd813
(fpga) Initial version of support for a free running timer
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Add initial version of changes needed to allow the timer to
optionally be free running.
This commit changes how the prescaler and timer counts.
Instead of down from a set value, they count from zero and up
to a set value.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-15 08:32:38 +02:00
Joachim Strömbergson
e961f46e79
Update Verilog version to 2005 for linting
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-04-24 08:44:08 +02:00
Joachim Strömbergson
e6eaad87dc
Update README with info about the timer API
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:25 +02:00
Joachim Strömbergson
9d188a2f7f
Add more info about how the timer works
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:24 +02:00
Joachim Strömbergson
7c9dfaf45a
Add testcase for the timer top level wrapper and clean up the tb
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:24 +02:00
Joachim Strömbergson
c185849ae4
Minor cleanup of README, testbench and Makefile
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:24 +02:00
Joachim Strömbergson
6137b88fe0
Add separate start, stop bits and running status bit in API
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-30 15:48:57 +01:00
Joachim Strömbergson
f020495695
Cleanup of tb for timer core
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-20 10:14:44 +01:00
Joachim Strömbergson
ddd969870e
Count from init values to one, not zero
2022-10-18 11:06:40 +02:00
Joachim Strömbergson
f6046d55a9
Change ADDR_CTRL to be a pulsed start_stop signal
2022-10-14 08:50:30 +02:00
Joachim Strömbergson
c3f7c5fb06
Ignore the prescaler if prescaler init value is zero
2022-10-13 16:24:03 +02:00
Joachim Strömbergson
2be934ee22
Restore start and stop bits, but clarify in documenation
2022-10-13 16:10:08 +02:00
Joachim Strömbergson
00d180d34e
Change to a single run bit and update access control
2022-10-13 14:58:39 +02:00
Joachim Strömbergson
82a64f2b2c
Remove DONE state that added one extra final cycle
2022-10-12 10:06:41 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores
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timer
touch_sense
figaro
uart
uds
2022-10-11 09:50:45 +02:00
Joachim Strömbergson
c90771fe19
Remove API access to current prescaler value
2022-10-06 15:56:13 +02:00
Joachim Strömbergson
715de60f4a
Make initial public release
2022-09-19 08:51:11 +02:00
