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339 commits

Author SHA1 Message Date
Daniel Jobson
b7ec4f9467
Implement preload_store 2024-11-21 09:48:51 +01:00
Daniel Jobson
53c63a1c7b
Temporarily override the blake2s trampoline 2024-11-21 09:48:51 +01:00
Daniel Jobson
fd84c69e9b
Wip syscall function. 
PoC of how a syscall could look like.
 2024-11-21 09:48:51 +01:00
Daniel Jobson
c7e0373793
WIP app storage calls 2024-11-21 09:48:51 +01:00
Daniel Jobson
496c5fb12a
preload_app: only allow mgmt app to store or delete 2024-11-21 09:48:51 +01:00
Daniel Jobson
2541790f21
WIP management app 2024-11-21 09:48:50 +01:00
Daniel Jobson
925962483a
fw: remove address-of operator (&) where it is not needed 
- `digest` is an array and hence the address of the first element is
  returned.
- This will keep it more consistent with the rest of the code base.
- Fixed misspelled comment.
 2024-11-21 09:48:50 +01:00
Daniel Jobson
c4d738a8d6
fw: use bool as return type for memeq 2024-11-21 09:48:50 +01:00
Daniel Jobson
5da60cba1a
Include authentication of preloaded app 2024-11-21 09:48:50 +01:00
Daniel Jobson
8c0f66282e
fw: break out trng and xorwow to rng.[ch] 2024-11-21 09:48:50 +01:00
Daniel Jobson
5188584fcf
fw: Break out htif functions for qemu to separate files 2024-11-21 09:48:50 +01:00
Daniel Jobson
ece53e044c
temp commit: Expose write functions to make development easier 2024-11-21 09:48:49 +01:00
Daniel Jobson
7f7820b698
Add fw state and fw cmd to trigger a start of a preloaded app 2024-11-21 09:48:49 +01:00
Daniel Jobson
9a1c9635f4
WIP auth app 2024-11-21 09:48:49 +01:00
Daniel Jobson
d859ca0357
WIP preload_app 2024-11-21 09:48:49 +01:00
Daniel Jobson
a0ce957f10
WIP partition table 2024-11-21 09:48:49 +01:00
Daniel Jobson
a873e7c211
Import spi.[ch] and flash.[ch] 2024-11-21 09:48:49 +01:00
Daniel Jobson
c00d5317b3
fw: Create compute_app_digest() function 2024-11-21 09:48:48 +01:00
Daniel Jobson
18ebdae030
Remove types.h in favor of standard libs such as stdint, stddef 2024-11-21 09:48:48 +01:00
Daniel Jobson
1941a22007
Doc: move implementation details of RAM scrambling to RAM core 2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
86aedcce69
Revise top-level README for the hardware design 
Merged information from fpga.md, and hence fpga.md is removed.
 2024-11-20 15:48:49 +01:00
Michael Cardell Widerkrantz
9f975bb66f
Add clangd target 
Create a compile_commands.json to help clangd for LSP.
 2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
fe8f0b1aa9
doc: Harmonize preformatted in tk1 core 
- No unnecessary indentation
- Mark API constants as preformatted
 2024-11-15 15:01:31 +01:00
Michael Cardell Widerkrantz
7043521ba9
Move high level system description to README in application_fpga 2024-11-15 15:01:31 +01:00
Jonas Thörnblad
7dc72ade04
Updated application_fpga.bin.sha256 with new hash 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
1b3bae334a
Change "rosc" references to "trng" 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
2364466a9e
Rename rosc.v to trng.v 2024-11-14 16:35:51 +01:00
Jonas Thörnblad
49189a3ba7
Fix typo 2024-11-14 16:35:50 +01:00
Jonas Thörnblad
1ea5db1179
Renamed sb_rgba_drv.v to sb_rgba_drv_sim.v 2024-11-14 16:35:29 +01:00
Jonas Thörnblad
2b89b28b82
Fix small TRNG testbench issues 2024-11-14 11:09:33 +01:00
Daniel Jobson
c4e8f6b6fb
Doc: fix typo of system mode in readme 2024-11-13 14:13:02 +01:00
Daniel Jobson
b90bbea1f6
Remove duplicate entries in default values assignment of tk1 api 
cpu_mon_en_we and cdi_mem_we was set twice
 2024-11-13 11:16:05 +01:00
Jonas Thörnblad
330146ba3a
Rename top level simulation files 
* Rename application_fpga_vsim.v and reset_gen_vsim.v to
  application_fpga_sim.v and reset_gen_sim.v
* Update Makefile
* Fix a typo
 2024-11-12 15:33:33 +01:00
Jonas Thörnblad
aea2e319eb
Harmonize the naming of firmware and app mode. 
- The API changes name from `_SWITCH_APP` to `_SYSTEM_MODE_CTRL`.
- The registers and wires changes name to `system_mode_*`, instead of a
  mix of `switch_app_*` and `fw_app_mode`.
 2024-11-12 15:13:59 +01:00
Jonas Thörnblad
c6e8b6930c
Add place and route script 
Run multiple threads of nextpnr-ice40 to find a seed that gives a
layout that meets timing.
 2024-10-22 15:20:39 +02:00
Jonas Thörnblad
8af048fb9a
Add yosys flags to optimize synthesis 
* -abc2, run two passes of 'abc' for slightly improved logic density
  * -device u, optimize timing for up5k device
  * -dff, run 'abc'/'abc9' with -dff (D flip flop) option

  Update digest of application_fpga.bin
 2024-10-22 12:46:12 +02:00
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
Jonas Thörnblad
e04aacda48
Add make target to format verilog code using verible-verilog-format 
Flags:
        --indentation_spaces=2
        --wrap_end_else_clauses=true

Verify flag, used in checkfmt, only returns error if the last file is
not formatted, temporary fix implemented with grep.
 2024-10-22 12:04:19 +02:00
Jonas Thörnblad
9e57296d91
Include SPI master in default build 
This prevents building without the SPI master, the intention is to use
a different method than if-defs, but it will be introduced at a later
stage.
 2024-10-16 12:50:32 +02:00
Daniel Jobson
cbb2ba7512
Doc: fix typo in tk1 core readme 2024-10-11 15:50:07 +02:00
Daniel Jobson
d9d41811bd
tb: fix tk1 testbench after name change 
This issue was introduced in commit 53c5e707, after name change of RAM
randomization API.
 2024-10-11 15:50:07 +02:00
Daniel Jobson
056ee4d3ee
Add make target to clean testbench files 
Add it as default in the contrib Makefile.
 2024-10-11 15:50:07 +02:00
Daniel Jobson
f13366538e
fw: Fix erroneous type in frame header 2024-10-09 15:52:00 +02:00
Jonas Thörnblad
0ea0eeb967
Fix makefile lines and tee exit status problem 
* Break long lines and use tab to indent
* Remove use of "tee" since it messes up the return status
* Remove the generated application_fpga_par.json if nextpnr-ice40 fails
  on timing.
* Change log file ending from .log to .txt
* Fix some spacing
 2024-10-08 16:07:17 +02:00
Daniel Jobson
bf1ac5c237
Remove YosysHQ copyright and fix name typo 
The removal is coordinated and approved by YosysHQ, and are removed
to keep our headers uniform. These files were written on behalf of
Tillitis.
Two typos was corrected as well.
 2024-09-30 15:01:31 +02:00
Daniel Jobson
81950ef7b2
fw: remove warning of missing prototypes when building with QEMU console 
enabled.
 2024-09-19 16:52:04 +02:00
Daniel Jobson
613316f53e
fw: simplify how to enable QEMU debug in firmware. 
- Remove the define `NOCONSOLE`, add define `QEMU_CONSOLE`
- Inverse the use of it, add the define to have QEMU debug output in fw.
- Add a make target `qemu_firmware.elf` which builds the firmware with
  QEMU console enabled.

Co-authored-by: Mikael Ågren <mikael@tillitis.se>
 2024-09-19 16:51:55 +02:00
Joachim Strömbergson
35052e50cb
FPGA: Move RAM address and data scrambling into the RAM module. 
Move the logic implementing the RAM address and data
	scrambling, descrambling into the RAM module. This cleans up
	the top level, and makes it easier to change the scrambling
	without chaning the top. In order to do correct scrambling the
	address to the RAM core must be 16 bits, not 15.

	Clean up some minor details at the top level, fixing text
        aligment and grouping of ports in instances.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-08-30 10:53:13 +02:00
Joachim Strömbergson
8d4ad120d6
Doc: Add README for the ROM core. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-08-29 16:06:59 +02:00
Joachim Strömbergson
2d769c5751
Doc: add README for the RAM. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-08-29 16:06:59 +02:00