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Author SHA1 Message Date
Joachim Strömbergson
c07c15a8b8
Update README to describe the new ROSC based TRNG 2022-10-19 09:37:58 +02:00
Michael Cardell Widerkrantz
cbe6d3db8d
Use the new firmware-only RAM for CDI computation 
To protect UDS we use a special firmware-only RAM for both the in
parameter to the blake2s() function and for the blake2s_ctx.
 2022-10-18 14:51:30 +02:00
Michael Cardell Widerkrantz
6d08a82c05
Pass the blake2s_ctx to blake2s() as arg 
Instead of allocating the blake2s_ctx in the blake2s() function we
pass it as a pointer as an argument to be able to better control where
the variable is in memory.
 2022-10-18 14:51:26 +02:00
Joachim Strömbergson
e0d68f3dae Merge branch 'main' of github.com:tillitis/tillitis-key1 2022-10-18 11:31:42 +02:00
Joachim Strömbergson
ddd969870e
Count from init values to one, not zero 2022-10-18 11:06:40 +02:00
Daniel Lublin
7129205cb0
Add fw_ram size to mem-include 2022-10-17 11:38:04 +02:00
Daniel Lublin
69c3f77e5e
testfw: tidy, clean-up, fmt 2022-10-17 11:15:26 +02:00
Joachim Strömbergson
f6046d55a9
Change ADDR_CTRL to be a pulsed start_stop signal 2022-10-14 08:50:30 +02:00
Joachim Strömbergson
c3f7c5fb06
Ignore the prescaler if prescaler init value is zero 2022-10-13 16:24:03 +02:00
Joachim Strömbergson
2be934ee22
Restore start and stop bits, but clarify in documenation 2022-10-13 16:10:08 +02:00
Joachim Strömbergson
50fbc8adc4
Update software description with timer API changes 2022-10-13 15:22:52 +02:00
Joachim Strömbergson
00d180d34e
Change to a single run bit and update access control 2022-10-13 14:58:39 +02:00
Joachim Strömbergson
5e5550461f
Removing confusing negation in message 2022-10-13 13:56:12 +02:00
Joachim Strömbergson
1b03459ab3
Remove app-accessible debug register from mta1 core 2022-10-13 13:51:19 +02:00
Joachim Strömbergson
51a22dc32c Merge branch 'fw_ram' 2022-10-13 13:16:53 +02:00
Joachim Strömbergson
1f2a585aba
Add test case for fw_ram 2022-10-13 13:16:11 +02:00
Joachim Strömbergson
8e493b6322
Debug fw_ram and add fw_app_mode access control 2022-10-13 13:14:10 +02:00
Joachim Strömbergson
b37b377a7e
Change optimization to Os since we want compact code 2022-10-13 09:26:49 +02:00
Michael Cardell Widerkrantz
99aabe89e9
Fix minor doc nits 2022-10-12 15:12:07 +02:00
Daniel Lublin
55c5081486
Adjust and document the firmware state-machine, including USS 
In particular, order of LOAD_USS and LOAD_APP_SIZE is not required, but
the need to send both is documented. This is followed up with adjustment
in the host programs' Go code, to try to reinforce this. LoadApp() will
take the secretPhrase parameter (to be hashed as USS), and loadUSS()
will be unexported.

Correct CMD/RSP lengths in pseudo-code.
 2022-10-12 15:12:07 +02:00
Joachim Strömbergson
5013338e50
Change to a more descriptive name 2022-10-12 11:14:46 +02:00
Joachim Strömbergson
192ce47fce
Fix #18 with incorrect clock frequency in analysis 2022-10-12 10:25:37 +02:00
Joachim Strömbergson
a9fd26da3b
Fix bit bit width mismatches 2022-10-12 10:21:50 +02:00
Joachim Strömbergson
f75860c2a2
Add link to SW page to the list of documents 
The page is linked from the system description page,
    but is probably hard to find.
 2022-10-12 10:14:07 +02:00
Joachim Strömbergson
c25fc0e7f2
Fix language nits 2022-10-12 10:10:48 +02:00
Joachim Strömbergson
6ce374cd97 Merge branch 'main' of github.com:tillitis/tillitis-key1 2022-10-12 10:08:16 +02:00
Joachim Strömbergson
82a64f2b2c
Remove DONE state that added one extra final cycle 2022-10-12 10:06:41 +02:00
Daniel Lublin
200ef26f36
Correct 2022-10-11 20:46:21 +02:00
Daniel Lublin
4d927ce426
Fix size_mismatch for testfw 2022-10-11 17:25:19 +02:00
Daniel Lublin
96746b2de0
Clarify BRAM_FW_SIZE 2022-10-11 17:25:00 +02:00
Joachim Strömbergson
cbf1104fed
Write whole byte, not nybbles 2022-10-11 17:05:21 +02:00
Joachim Strömbergson
a51619e5b7
Add fw_ram module 2022-10-11 16:58:26 +02:00
Joachim Strömbergson
24cf80af32
Remove redundant spram module 2022-10-11 13:27:57 +02:00
Joachim Strömbergson
7e0692b150
Replace FiGaRO based TRNG with new ROSC based TRNG 2022-10-11 13:17:04 +02:00
Joachim Strömbergson
af36a40f3e Merge branch 'new_trng' 2022-10-11 13:00:13 +02:00
Joachim Strömbergson
5087a67376
Reduce FW ROM size to 6 kByte 2022-10-11 12:54:44 +02:00
Joachim Strömbergson
4b929fedf2 Merge branch 'name_version' 2022-10-11 11:30:47 +02:00
Joachim Strömbergson
1439e4a587
Remove name, version info about cores from SW description 2022-10-11 11:28:40 +02:00
Joachim Strömbergson
87dab3fe6d
Remove name, version addresses for cores 2022-10-11 09:55:56 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores 
timer
       touch_sense
       figaro
       uart
       uds
 2022-10-11 09:50:45 +02:00
Joachim Strömbergson
cdbe71d40d
Add new ROSC based TRNG with VN decorrelation 2022-10-11 08:45:06 +02:00
Joachim Strömbergson
4ed27b4460
Add new rosc based entropy source 2022-10-08 18:37:48 +02:00
Michael Cardell Widerkrantz
df7a26c28c
Compile firmware with -DNOCONSOLE 2022-10-07 11:19:53 +02:00
Joachim Strömbergson
c90771fe19
Remove API access to current prescaler value 2022-10-06 15:56:13 +02:00
Joachim Strömbergson
cc59d8dc93
Update verilator top level module to match rom module changes 2022-10-06 13:59:01 +02:00
Joachim Strömbergson
f80aaa4e8a Merge branch 'main' of github.com:tillitis/tillitis-key1 2022-10-06 13:25:35 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following: 
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
 2022-10-06 13:23:30 +02:00
Daniel Lublin
429ac6877e
Note about the importance of releases; clarify some docs 2022-10-04 13:17:37 +02:00
Daniel Lublin
2bb62af183
Update bit divisor calc in verilator's uart to our current 18 MHz 2022-10-03 13:11:53 +02:00
Joachim Strömbergson
6f31bbe37a Merge branch 'main' of github.com:tillitis/tillitis-key1 2022-10-03 12:56:41 +02:00