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Update bit divisor calc in verilator's uart to our current 18 MHz

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Daniel Lublin 2022-10-03 13:11:53 +02:00
parent 6f31bbe37a
commit 2bb62af183
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1 changed files with 3 additions and 4 deletions
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7
hw/application_fpga/tb/application_fpga_verilator.cc
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@ -24,10 +24,9 @@
#include "Vapplication_fpga.h"
#include "verilated.h"
// Joachim says:
// Clock: 12 MHz, 38400 bps
// Divisor = 12*10E6 / 38400 = 312
#define BIT_DIV 312
// Clock: 18 MHz, 38400 bps
// Divisor = 18*10E6 / 38400 = 468.75 ~ 469
#define BIT_DIV 469
struct uart {
int bit_div;