Merge branch 'main' of github.com:tillitis/tillitis-key1

This commit is contained in:
Joachim Strömbergson 2022-10-12 10:08:16 +02:00
commit 6ce374cd97
2 changed files with 10 additions and 7 deletions

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@ -26,8 +26,8 @@ specifications:
should be the target.
* 4 SPRAM x 32 KB => 128 KB RAM for application/software
[^1]: Embedded Block RAM residing in the FPGA, can configured as RAM
or ROM.
[^1]: Embedded Block RAM (also BRAM) residing in the FPGA, can
configured as RAM or ROM.
## Introduction

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@ -22,7 +22,8 @@ YOSYS_PATH ?=
NEXTPNR_PATH ?=
ICESTORM_PATH ?=
# Size in 32-bit words
# Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
# bits wide; an EBR is 128 32-bits words)
BRAM_FW_SIZE ?= 1536
PIN_FILE ?= application_fpga_mta1_usb_v1.pcf
@ -94,11 +95,13 @@ all: application_fpga.bin
# The size_mismatch target make sure that we don't end up with an
# incorrect BRAM_FW_SIZE
# -------------------------------------------------------------------
size_mismatch: firmware.elf
%_size_mismatch: %.elf phony_explicit
@test $$($(SIZE) $< | awk 'NR==2{print $$4}') -le $$(( 32 / 8 * $(BRAM_FW_SIZE) )) || \
(echo "The 'BRAM_FW_SIZE' variable needs to be increased" && false)
.PHONY: size_mismatch
# can't make implicit rule .PHONY
phony_explicit:
.PHONY: phony_explicit
#-------------------------------------------------------------------
# Firmware generation.
@ -119,9 +122,9 @@ testfw.elf: $(TESTFW_OBJS) $(P)/fw/mta1_mkdf/firmware.lds
bram_fw.hex:
$(ICESTORM_PATH)icebram -v -g 32 $(BRAM_FW_SIZE) > $@
firmware.hex: firmware.bin size_mismatch
firmware.hex: firmware.bin firmware_size_mismatch
python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
testfw.hex: testfw.bin size_mismatch
testfw.hex: testfw.bin testfw_size_mismatch
python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
%.bin: %.elf