Commit Graph

16 Commits

Author SHA1 Message Date
Jonas Thörnblad
3514d7ef3c
FPGA: Format verilog code 2024-10-22 12:04:19 +02:00
Joachim Strömbergson
75b028505f
FPGA: Increase clock frequency to 21 MHz
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-20 13:45:00 +02:00
Joachim Strömbergson
e961f46e79
Update Verilog version to 2005 for linting
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-04-24 08:44:08 +02:00
blaufish
cced6aec31
Explicity make uart_core.rx_data a wire (#140) 2023-08-16 10:43:04 +02:00
Joachim Strömbergson
97e3e25d98
Update the UART README with info about the core and its API
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:25 +02:00
Joachim Strömbergson
704d67c8ab
Add Makefile to build sim. Debug sim build
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:25 +02:00
Joachim Strömbergson
3eb5b7879c Add API address to read out number of bytes in Rx FIFO
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-03-07 08:22:27 +01:00
Joachim Strömbergson
9ce2b8a84a
Only accept tx data when the core is ready
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-02 13:10:40 +01:00
Joachim Strömbergson
8061491f6e
Cleanup, and use fifo_empty to indicate data available 2022-10-28 13:12:47 +02:00
Joachim Strömbergson
24d8680772
Improve detection of empty and full FIFO 2022-10-28 13:09:21 +02:00
Joachim Strömbergson
0eacbca2f9
Increase size of RX-FIFO to 512 bytes 2022-10-28 12:48:13 +02:00
Daniel Lublin
675fa1087f
Raise bps to 62500 2022-10-21 14:10:41 +02:00
Joachim Strömbergson
3f44b999ac
Remove name, version from several cores
timer
       touch_sense
       figaro
       uart
       uds
2022-10-11 09:50:45 +02:00
Joachim Strömbergson
c35e7680ea
Squashed commit of the following:
Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port
2022-10-06 13:23:30 +02:00
Joachim Strömbergson
f41573cc60
Update bit counter to match 18 MHz clock frequency 2022-09-30 10:04:37 +02:00
Joachim Strömbergson
715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00