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tillitis-key/hw/application_fpga/core/uart
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Joachim Strömbergson 0eacbca2f9
Increase size of RX-FIFO to 512 bytes
2022-10-28 12:48:13 +02:00
..
rtl
Increase size of RX-FIFO to 512 bytes
2022-10-28 12:48:13 +02:00
tb
Make initial public release
2022-09-19 08:51:11 +02:00
LICENSE
Make initial public release
2022-09-19 08:51:11 +02:00
README.md
Make initial public release
2022-09-19 08:51:11 +02:00

README.md

uart

A simple universal asynchronous receiver/transmitter (UART) core implemented in Verilog.

Status

The core is completed and has been used in several FPGA designs.