Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-12-14 02:14:23 -05:00
Code Issues Packages Projects Releases Wiki Activity
0eacbca2f9
tillitis-key/hw/application_fpga/core/uart
History
Joachim Strömbergson 0eacbca2f9
Increase size of RX-FIFO to 512 bytes
2022-10-28 12:48:13 +02:00
..
rtl Increase size of RX-FIFO to 512 bytes 2022-10-28 12:48:13 +02:00
tb Make initial public release 2022-09-19 08:51:11 +02:00
LICENSE Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

README.md

uart

A simple universal asynchronous receiver/transmitter (UART) core implemented in Verilog.

Status

The core is completed and has been used in several FPGA designs.