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tillitis-key/hw/application_fpga/core/uart
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Joachim Strömbergson 704d67c8ab
Add Makefile to build sim. Debug sim build 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-07-04 09:04:25 +02:00
..
rtl Add API address to read out number of bytes in Rx FIFO 2023-03-07 08:22:27 +01:00
tb Add Makefile to build sim. Debug sim build 2023-07-04 09:04:25 +02:00
toolruns Add Makefile to build sim. Debug sim build 2023-07-04 09:04:25 +02:00
LICENSE Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

README.md

uart

A simple universal asynchronous receiver/transmitter (UART) core implemented in Verilog.

Status

The core is completed and has been used in several FPGA designs.