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Joachim Strömbergson 715de60f4a Make initial public release 2022-09-19 08:51:11 +02:00
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rtl Make initial public release 2022-09-19 08:51:11 +02:00
tb Make initial public release 2022-09-19 08:51:11 +02:00
LICENSE Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

README.md

uart

A simple universal asynchronous receiver/transmitter (UART) core implemented in Verilog.

Status

The core is completed and has been used in several FPGA designs.