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4003d6a1c0
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51 Commits

Author SHA1 Message Date
Joachim Strömbergson
4003d6a1c0
FPGA: Improve SPI testing 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-07-11 09:38:24 +02:00
Joachim Strömbergson
3d8491af71
FPGA: Move sample point to not miss MISO lsb 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-07-11 09:37:46 +02:00
Joachim Strömbergson
53c5e70795
FPGA: Update names for RAM randomization API 
Update:
- README
- testbench
- Symbolic names and variables in fw
- registers
- port name and wires
- Update fpga and fw digests

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-07-10 13:45:26 +02:00
Joachim Strömbergson
816718307f
fpga: Fix nits in constant value specification 
Remove the preceeding zero in the constant expression
      that cause the simulator to warn about incorrect
      bit size.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-07-09 10:51:10 +02:00
Joachim Strömbergson
c271b48a53
FPGA: Remove redundant clock cycle counter 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-06-19 15:48:24 +02:00
Joachim Strömbergson
ec77b15eb8
FPGA: Increase SPI speed 
- Change SPI clock from 16 CPU cyles/flank to one cycle/flank
- Remove separate flank length wait states in the FSM

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-06-19 15:48:07 +02:00
Joachim Strömbergson
8ce07683f8
FPGA: SPI-master improvements 
- Changed FSM states to localparams
- Added localparam for SPI clock divisor
- Added internal signal for divisor reached
- Improved comments to clarify code
- Fixed some minor textual nits

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-06-19 11:51:44 +02:00
Joachim Strömbergson
f61d254fda
Adding testbench and simulation targets for the SPI master. 2024-06-11 15:28:29 +02:00
Joachim Strömbergson
3bc2453287
A construction of a minimal SPI master. 
- NOTE: This is an optional feature, not built by default. Not included
  in the tk1 for sale at Tillitis shop.
- This makes it possible to interface the SPI flash onboard TKey.
- To include the SPI master in the build, use `make application_fpga.bin
  YOSYS_FLAG=-DINCLUDE_SPI_MASTER`.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-06-11 15:28:29 +02:00
Joachim Strömbergson
09df7ae97f
FPGA: Fix linting of tk1 core 
Add simultion models of udi_rom and sb_rbga_drv
      to lint-top target.

      Add ignore statements in tb_sb_rgba_drv to silence
      Verilator on parameters and signals not used in
      the sim model.

      Use RGBLEDEN in simulation model

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-06-10 14:22:59 +02:00
Joachim Strömbergson
cadf8e9849
FPGA: Add sim model of udi_rom 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-06-07 12:06:40 +02:00
Joachim Strömbergson
e961f46e79
Update Verilog version to 2005 for linting 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-04-24 08:44:08 +02:00
Michael Cardell Widerkrantz
3cf218469c
hw/tool: UDI/UDS storage 
Describe how the UDI and UDS are actually stored in the FPGA, how they
are accessed, and how they are initialled by the patch_uds_udi.py
script.

Co-authored-by: Joachim Strömbergson <joachim@assured.se>
 2024-04-03 11:27:00 +02:00
Joachim Strömbergson
de668a0244
Clean up code and silence warnings after linting 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-03-20 16:39:53 +01:00
Joachim Strömbergson
bbde62d3f5
Add PINMISSING lint ignore for I1 and I2 SB_LUT4 cells 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-03-20 16:39:52 +01:00
Joachim Strömbergson
8731908cb1
Support incremental builds for the bitstream. 
By patching the UDS and UDI into an already built bitstream, it is now
not necessary to rebuild the entire build flow when changing the UDS
and the UDI. This lowers re-build times significantly.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-03-20 16:39:45 +01:00
Joachim Strömbergson
8784a24b33
Change cpu_monitor to security_monitor and to also check RAM 
Change name of cpu_monitor to security_monitor and increase its
functionality to include RAM access violations. If addresses in RAM
but outside of physical RAM is accessed in any way the
security_monitor traps the CPU in the same way as it already did for
execution violations.
 2024-03-20 14:36:55 +01:00
Joachim Strömbergson
3fb6d66cf3
Add set-only register for the force_trap signal to ensure 
that the device must be reset to get out of trap. This
change also breaks a critical path.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2024-03-20 14:36:55 +01:00
Joachim Strömbergson
a517552c85
Update README with info about the core functions 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:28 +02:00
Joachim Strömbergson
bc7dfea9c4
Add test9: EXE monitor control and detection 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:28 +02:00
Joachim Strömbergson
4644c79cbd
Adding test 8: GPIO test 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:28 +02:00
Joachim Strömbergson
394e437c91
Add test7: Control of LED RGB outputs. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:27 +02:00
Joachim Strömbergson
480f4e3d45
Add test6: Test that RAM ASLR and SCRAMBLE registers can be set by fw 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:27 +02:00
Joachim Strömbergson
d70937c11b
Improved messaging from the testbench 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:27 +02:00
Joachim Strömbergson
59af60bdd5
Add test4: writing and reading blake2s entry point 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:27 +02:00
Joachim Strömbergson
dc2903a5b4
Update test3 to check that writing to CDI works when in fw mode 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:27 +02:00
Joachim Strömbergson
16a91bfdd5
Adding test 3: Reading out the CDI 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:27 +02:00
Joachim Strömbergson
1f47991ac2
Add test2: Read out UDI 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:27 +02:00
Joachim Strömbergson
6d9890d050
Add test1: Read out name and version 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:26 +02:00
Joachim Strömbergson
49eac9d101
Complete init of DUT and input, output display 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:26 +02:00
Joachim Strömbergson
1909833952
Add header with info and license 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:26 +02:00
Joachim Strömbergson
b1993742bb
Fix testbench buik including DUT instantiation 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:26 +02:00
Joachim Strömbergson
2fb61bba73
Add UDI used during simulation 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:26 +02:00
Joachim Strömbergson
cb2fd573b3
Add dummy LED macro driver module needed for simulation 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:26 +02:00
Joachim Strömbergson
61598f57e5
Add initial version of testbench annd Makfile for building sim target 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-07-04 09:04:26 +02:00
Joachim Strömbergson
000b7644b5
Update fw ram last address to match new mem size 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-08 13:31:45 +01:00
Joachim Strömbergson
2e2ca04ab7
Bump FPGA design version to 5 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-07 12:30:10 +01:00
Joachim Strömbergson
d075cc72c3
Manually merged changes for scrambling 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-07 10:42:59 +01:00
Joachim Strömbergson
4db4e39205
Clarify the purpose and functionality of the tk1 core 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-07 08:20:18 +01:00
Joachim Strömbergson
6f327d2ff9
Block changing of monitor addresses when enabled 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
66ebe5089a
Add fw_ram as always active exe monitor area 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
5c05ae657e
exe monitor can only be enabled, not disabled 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
7612d00ccf
Feed CPU illegal instruction to trigger trap 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:55 +01:00
Joachim Strömbergson
86ea45e10a
Add CPU execution monitor 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 15:41:53 +01:00
Joachim Strömbergson
e514f778b2 Remove stray variable for blake2s address update 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 11:32:38 +01:00
Joachim Strömbergson
adcccc44de Change reset value for the trap led to black 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 11:32:38 +01:00
Joachim Strömbergson
d335dd708a Add HW to detect trap in cpu and signal using the LEDs 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-03-06 11:32:38 +01:00
Joachim Strömbergson
caeee54e19
Change LED reset value to black 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2023-02-27 13:21:51 +01:00
Joachim Strömbergson
5c74a0727c
Lock down access to UDI in app mode 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2022-12-20 12:05:56 +01:00
Joachim Strömbergson
a48dc7cbbb
Add reg writable from FW, readable from app for blake2s entry 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2022-12-08 16:16:15 +01:00