15 Commits

Author	SHA1	Message	Date
Joachim Strömbergson	1aa2d7bd95	Merge branch 'pll'	2022-09-30 10:06:48 +02:00
Joachim Strömbergson	f41573cc60	Update bit counter to match 18 MHz clock frequency	2022-09-30 10:04:37 +02:00
Daniel Lublin	99efb78ed8	Receive USS and hash into CDI ... - We're OK with USS not being loaded, and use an all-zero USS if so. - We require USS to be loaded before app_size (if at all).	2022-09-29 14:58:23 +02:00
Daniel Lublin	df67966d8f	Be consistent and check for errors first	2022-09-28 10:34:48 +02:00
Joachim Strömbergson	f09ff87f9e	Support DIV instructions and catch illegal instructions	2022-09-28 10:29:00 +02:00
Joachim Strömbergson	90a57c4948	Use PLL and global buffer to increas clock speed	2022-09-27 16:41:38 +02:00
Joachim Strömbergson	610522201b	Remove AXI and WB interface modules	2022-09-27 09:48:54 +02:00
Daniel Lublin	10b7951933	Let verilator print when touched by kill -USR1	2022-09-21 11:25:13 +02:00
Daniel Lublin	8066c1092e	Make fmt output changes that will be made	2022-09-21 10:13:39 +02:00
Björn Töpel	2f59eaacdc	Add default values to tpt.py ... Provide default values for vendor id, product id, revision number, and serial number.	2022-09-21 09:49:07 +02:00
Joachim Strömbergson	43ec0641c0	Change uss to ent to remove confusion	2022-09-21 09:38:44 +02:00
Daniel Lublin	40803993e1	Make synth.json depend on data/{uds,udi}.hex; revise docs	2022-09-20 16:37:04 +02:00
Joachim Strömbergson	9d5e1c5ad5	Remove debug output of arguments	2022-09-19 12:37:27 +02:00
Joachim Strömbergson	3110d1218d	Silence lint re missing pins on cell instances	2022-09-19 10:35:49 +02:00
Joachim Strömbergson	715de60f4a	Make initial public release	2022-09-19 08:51:11 +02:00