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tillitis-key/hw/application_fpga
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Daniel Lublin 99efb78ed8
Receive USS and hash into CDI 
- We're OK with USS not being loaded, and use an all-zero USS if so.
- We require USS to be loaded before app_size (if at all).
2022-09-29 14:58:23 +02:00
..
core
Remove AXI and WB interface modules
2022-09-27 09:48:54 +02:00
data
Make initial public release
2022-09-19 08:51:11 +02:00
fw
Receive USS and hash into CDI
2022-09-29 14:58:23 +02:00
rtl
Support DIV instructions and catch illegal instructions
2022-09-28 10:29:00 +02:00
tb
Let verilator print when touched by kill -USR1
2022-09-21 11:25:13 +02:00
tools
Add default values to tpt.py
2022-09-21 09:49:07 +02:00
Makefile
Make synth.json depend on data/{uds,udi}.hex; revise docs
2022-09-20 16:37:04 +02:00