tillitis-key/hw/application_fpga
2022-09-21 10:13:39 +02:00
..
core Silence lint re missing pins on cell instances 2022-09-19 10:35:49 +02:00
data Make initial public release 2022-09-19 08:51:11 +02:00
fw Make fmt output changes that will be made 2022-09-21 10:13:39 +02:00
rtl Silence lint re missing pins on cell instances 2022-09-19 10:35:49 +02:00
tb Make initial public release 2022-09-19 08:51:11 +02:00
tools Add default values to tpt.py 2022-09-21 09:49:07 +02:00
Makefile Make synth.json depend on data/{uds,udi}.hex; revise docs 2022-09-20 16:37:04 +02:00