Daniel Lublin df67966d8f

Be consistent and check for errors first

2022-09-28 10:34:48 +02:00

..

core

Remove AXI and WB interface modules

2022-09-27 09:48:54 +02:00

data

Make initial public release

2022-09-19 08:51:11 +02:00

fw

Be consistent and check for errors first

2022-09-28 10:34:48 +02:00

rtl

Support DIV instructions and catch illegal instructions

2022-09-28 10:29:00 +02:00

tb

Let verilator print when touched by kill -USR1

2022-09-21 11:25:13 +02:00

tools

Add default values to tpt.py

2022-09-21 09:49:07 +02:00

Makefile

Make synth.json depend on data/{uds,udi}.hex; revise docs

2022-09-20 16:37:04 +02:00