tillitis-key/hw/application_fpga
2022-09-30 10:04:37 +02:00
..
core Update bit counter to match 18 MHz clock frequency 2022-09-30 10:04:37 +02:00
data Make initial public release 2022-09-19 08:51:11 +02:00
fw Make fmt output changes that will be made 2022-09-21 10:13:39 +02:00
rtl Use PLL and global buffer to increas clock speed 2022-09-27 16:41:38 +02:00
tb Let verilator print when touched by kill -USR1 2022-09-21 11:25:13 +02:00
tools Add default values to tpt.py 2022-09-21 09:49:07 +02:00
Makefile Use PLL and global buffer to increas clock speed 2022-09-27 16:41:38 +02:00